Abstract: A data storage apparatus, memory controller, and or method operation method may be disclosed. The memory controller may include an address generator configured to generate an operation target address and a destination address. The memory controller may be configured to output the operation target address and the destination address. The memory controller may include a data processor configured to receive the operation target address, read data by accessing the corresponding address of the operation target address, perform an operation on the read data, access the destination address, and write a result of the operation in the accessed destination address.

Abstract: A data storage apparatus in accordance with an embodiment may include a memory device, a memory controller, and a media controller. The memory device may store data. The memory controller may output a packetized request signal for the memory device and receive a response signal to the packetized request signal according to a predetermined protocol. In response to a request packet provided from the memory controller, the media controller may generate a media command corresponding to the memory device, perform a read or write operation on the memory device, generate a response packet upon completion of the read or write operation, and transmit the generated response packet to the memory controller.

Abstract: A memory system may include a memory module accessed by a first address, a memory controller configured to provide a read or write command for the memory module according to a host request, and a memory buffer accessed by a second address. The memory buffer may include a register file having two or more entry spaces corresponding to interleaving units of the memory module, and the two or more entry spaces may be positioned in different address areas which are accessible at the same time.

Abstract: A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.

Abstract: A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region.

Abstract: A semiconductor memory device includes a memory cell array including a main cell array and a repair cell array, a command controller that controls an input/output operation of the memory cell array, an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written, an ECC that performs a parity operation for data input/output to the memory cell array, an address table that associates an address, at which a fail has occurred when the fail has occurred in the ECC, with a number of times of occurrence of the fail, and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored.

Abstract: A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region.

Abstract: An apparatus and method for performing a system evaluation such as real-time virus scan/diagnosis/cure in order to improve system performance in a portable terminal are provided. The apparatus includes an operation monitoring unit for determining an idle state duration and an active state duration by monitoring an operation of the portable terminal, and a pattern analysis unit for defining the idle state duration as a system evaluation duration.

Abstract: A display apparatus of magnetic flux density for detecting an internal crack of a metal or a shape of the metal includes a three-dimensional magnetic flux focusing unit installed near the metal, for concentrating magnetic flux generated by the metal, a magnetic flux density measurement unit installed near the magnetic flux focusing unit, for measuring changes in magnetic flux density concentrated by the magnetic flux focusing unit, and a display unit electrically connected with the magnetic flux measurement unit, for real-time displaying and storing changes in the magnetic flux density.

Abstract: A display apparatus of magnetic flux density for detecting an internal crack of a metal or a shape of the metal includes a three-dimensional magnetic flux focusing unit installed near the metal, for concentrating magnetic flux generated by the metal, a magnetic flux density measurement unit installed near the magnetic flux focusing unit, for measuring changes in magnetic flux density concentrated by the magnetic flux focusing unit, and a display unit electrically connected with the magnetic flux measurement unit, for real-time displaying and storing changes in the magnetic flux density.