Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.

Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.

Abstract: A process for manufacturing a dynamic random access memory (DRAM) cell wherein an improvement is made in an occurrence of soft errors in operation of a memory device, said soft errors resulting from alpha particles being produced from uranium-series materials included in fabricating materials during fabrication of memory chips, especially in the package of the chip. In a single transistor memory cell, through forming boron layers below a storage capacitor region and below a drain region of the transistor coupled with a bit line, a barrier is formed against the minority carriers resulting from the alpha particles within the substrate. Also, through enlarging the storage capacitor region toward a field oxide layer just around the capacitor perimeter, a capacitance of the storage capacitor is increased so that the influence of the soft errors is negligible.