Abstract: A display device includes a plurality of first constant voltage lines extended along a first direction and arranged along a second direction crossing the first direction, a plurality of second constant voltage lines extended along the second direction and arranged along the first direction, a first overlap area in which the plurality of first constant voltage lines and the plurality of second constant voltage lines overlap and contact each other, and a second overlap area in which the plurality of first constant voltage lines and the plurality of second constant voltage lines overlap and are insulated from each other.

Abstract: Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of the array for the multiplication of the input with the weight. To perform a multiply and accumulate operation, the results of the multiplications are accumulated by adders connected to sense amplifiers along the bit lines of the array. The adders can be configured to multiple levels of precision, so that the same structure can accommodate weights and activations of 8-bit, 4-bit, and 2-bit precision.

Abstract: Provided is a surface-treated steel sheet including: a steel sheet; and a corrosion-resistant film layer formed on at least one surface of the steel sheet. The corrosion-resistant film layer includes a product formed by a hydrolysis reaction of silica and an alkoxy silane and an acrylate-based polymer, comprises 25 to 65 wt % of carbon (C), 20 to 70 wt % of silicon (Si), and 1 to 40 wt % of oxygen (O), and in the corrosion-resistant film layer, a ratio of silicon (Si) to oxygen (O) (Si—O bonding) and silicon (Si) to carbon (C) (Si—C bonding) is 80 to 95 wt %:5 to 20 wt %.

Abstract: A vibration measurement error determination method according to an embodiment of the present invention comprises: a vibration data acquisition step for acquiring vibration data by measuring a vibration generated in a structure; a first determination step for determining, on the basis of a preset error data selection rule, whether the vibration data is data generated by a measurement error; a second determination step for using a machine-learning algorithm to determine whether the vibration data is data generated by a measurement error; and a final determination step for determining, on the basis of the results determined in the first determination step and the second determination step, whether the vibration data is data generated by a measurement error.

Abstract: A layer jamming driving device is proposed, which includes an enclosure made of a variable material; and layer stacked structures having a plurality of layers stacked inside the enclosure, wherein the layer stacked structures can be coupled so as to be slidable and rotatable with respect to each other.

Abstract: Provided is a composition for steel sheet surface coating, the composition comprising colloidal silica, a silane, a monomer, an organic resin, an acidity adjuster, a long-term corrosion-resistance improver, and a solvent; and a steel sheet coated with the composition. The steel sheet has excellent acid resistance, and maintains thickness uniformity thereof even when exposed to an acid for an extended period of time.

Abstract: The present invention relates to a dry powder inhaler. The dry powder inhaler includes an inhaler housing, a drug container configured to be provided in the inhaler housing and accommodate the dry powder drug, a drug inlet configured to be disposed above the drug container and through which the dry powder drug is inhaled, and a mesh network configured to be installed on a path of the drug inlet and have a mesh part for collision with the dry powder drug formed therein.

Abstract: In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.

Abstract: An anti-icing honeycomb core composite manufactured by forming an electromagnetic wave absorption layer by using dielectric fiber, molding the electromagnetic wave absorption layer into a honeycomb core structure by using a molded part including a first base, a second base, and an inner block, hardening the honeycomb core structure, and removing the molded part. The molding step includes first stacking, on the first base including a plurality of grooves in which the inner blocks each having a hexagonal column shape are able to be seated, a plurality of the inner blocks and a plurality of the electromagnetic wave absorption layers as the honeycomb core structure so that the electromagnetic wave absorption layer is disposed between the plurality of inner blocks, and second stacking covering the inner blocks and the electromagnetic wave absorption layers stacked on the first base with the second base having the same shape as the first base.

Abstract: Disclosed is an automatic alignment method of a high-pressure gas container in which a high-pressure gas container is loaded on a lift of a cabinet so as to supply a gas from a fabrication (FAB) process facility of a semiconductor to a wafer production line, and then, the high-pressure gas container loaded on the lift is raised, and an end cap of the high-pressure gas container and the center of a connector holder of a gas pipe are automatically aligned.

Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

Abstract: The present disclosure relates to a sub-nanometric particles-metal organic framework complex including a multi-shell hollow metal organic framework (MOF) and sub-nanometric particles (SNPs), and a method of preparing the same.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

Abstract: Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

Abstract: An anti-icing honeycomb core composite manufactured by forming an electromagnetic wave absorption layer by using dielectric fiber, molding the electromagnetic wave absorption layer into a honeycomb core structure by using a molded part including a first base, a second base, and an inner block, hardening the honeycomb core structure, and removing the molded part. The molding step includes first stacking, on the first base including a plurality of grooves in which the inner blocks each having a hexagonal column shape are able to be seated, a plurality of the inner blocks and a plurality of the electromagnetic wave absorption layers as the honeycomb core structure so that the electromagnetic wave absorption layer is disposed between the plurality of inner blocks, and second stacking covering the inner blocks and the electromagnetic wave absorption layers stacked on the first base with the second base having the same shape as the first base.

Abstract: Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.

Abstract: Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for inferencing to be performed more quickly and with less power. In a high performance and energy efficiency mode, a reduced rank for the SVD matrices stored on a memory die is determined and used to increase performance and reduce power needed for an inferencing operation.

Abstract: Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.