Patents by Inventor Won Hyung KANG

Won Hyung KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240166991
    Abstract: The present disclosure relates to a cell culture medium composition and a preparation method therefor. By replacing an animal serum with a Spirulina hydrolysate, cell growth can be induced and cell proliferation can be promoted to a level greater than or equal to that of a medium containing an animal serum, while significantly reducing the added amount of animal serum.
    Type: Application
    Filed: April 1, 2022
    Publication date: May 23, 2024
    Inventors: Do-Hyung KANG, Young-Deuk LEE, Woon-Yong CHOI, Youn Sik JEONG, Areumi PARK, Yeon-Ji LEE, Tae-Ho KIM, Won-Kyu LEE, Yong-Kyun RYU
  • Publication number: 20240158273
    Abstract: The present disclosure provides a resource-circulation-type and eco-friendly livestock manure treatment method, and a system for producing algal biomass used therein, the method being capable of: preventing water pollution while allowing livestock liquid fertilizer to be treated on the basis of a biological process; producing algal biomass; and supplying the produced algal biomass to livestock feed and farms.
    Type: Application
    Filed: April 1, 2022
    Publication date: May 16, 2024
    Inventors: Do-Hyung KANG, Yong-Kyun RYU, Won-Kyu LEE, Woon-Yong CHOI, Tae-Ho KIM, Yeon-Ji LEE, Areumi PARK, Youn Sik JEONG
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Patent number: 10615162
    Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kwan Yu, Won Hyung Kang, Hyo Jin Kim, Sung Bu Min
  • Publication number: 20180358358
    Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.
    Type: Application
    Filed: November 2, 2017
    Publication date: December 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kwan YU, Won Hyung KANG, Hyo Jin KIM, Sung Bu MIN