Abstract: The present invention relates to a nanocomposite device comprising a polymeric matrix, semiconducting nanoparticles, and a semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs. In addition, the present invention relates to a method of making a nanocomposite device. The method includes providing a mixture comprising a polymer, semiconducting nanoparticles, and a semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs or a soluble precursor thereof, depositing the mixture on a substrate, and treating the mixture under conditions effective to produce a nanocomposite device comprising the polymeric matrix, semiconducting nanoparticles, and the semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs. Thin film devices including the nanocomposite device are also disclosed.

Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Abstract: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Abstract: A semiconductor structure includes a material layer on a substrate and to be patterned, an amorphous carbon layer on the material layer to be patterned, an N-free anti-reflective layer on the amorphous carbon layer, and a photoresist layer on the N-free anti-reflective layer. The N-free anti-reflective layer contains SiCXOYHZ as a main element. Related methods of patterning semiconductor structures also are provided.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Abstract: Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

Abstract: A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate, forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.

Abstract: A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.

Abstract: An integrated circuit device includes a substrate that has a pattern formed thereon. The pattern may have two or more mesa regions. A spin on glass insulation layer is disposed between the pair of mesa regions and a second insulation layer is disposed on the spin on glass insulation layer, at least partially in the gap between the mesas, to form a composite insulation layer. The second insulation layer may be SiO2, SiN, and/or SiON. The spin on glass may be polysilazane, hydro silsesquioxane, silicate, and/or methyl silsesquioxane.

Abstract: Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

Abstract: Disclosed is a method for forming interconnection lines using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer. A HSQ layer is formed over a semiconductor substrate and an entire surface of the HSQ layer is subjected to plasma treatment. It is then possible to pattern the HSQ layer using photo etching, for the bond structure density of an upper part of the HSQ layer has been increased due to the plasma treatment. An opening is formed by patterning the treated HSQ layer and then a conductive layer filling the opening is formed. In this manner, a multilayer interconnection structure can be formed with a low dielectric layer made of HSQ, thereby reducing the resistance-capacitance (RC) delay.

Abstract: A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer, forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.