Abstract: A nanopore device for detecting charged biopolymer molecules and defining a nanochannel, includes a first gating nanoelectrode addressing a first end of the nanochannel. The device also includes a second gating nanoelectrode addressing a second end of the nanochannel opposite the first end. The device further includes a first sensing nanoelectrode addressing a first location in the nanochannel between the first and second ends.

Abstract: A nanopore device for detecting charged biopolymer molecules and defining a nanochannel, includes a first gating nanoelectrode addressing a first end of the nanochannel. The device also includes a second gating nanoelectrode addressing a second end of the nanochannel opposite the first end. The device further includes a first sensing nanoelectrode addressing a first location in the nanochannel between the first and second ends.

Abstract: A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer.

Abstract: A photodetector using graphene includes: a gate electrode; a graphene channel layer which is opposite to and spaced apart from the gate electrode and does not have ?-binding; a first electrode which contacts a first side of the graphene channel layer; and a second electrode which contacts a side of the graphene channel layer, where the first and second sides are opposite to each other, and where the graphene channel layer includes a first graphene layer and a first nanoparticle disposed on the first graphene layer. The first graphene layer may include a single graphene layer, or the first graphene layer may include a plurality of single graphene layers, which is sequentially stacked and does not have ?-binding.

Abstract: A photodetector includes a substrate, a graphene layer disposed on the substrate, a first electrode disposed on the graphene layer, and a second electrode disposed on the graphene layer, where the first and second electrodes are spaced apart from each other, and where each of the first and second electrodes comprises a complex transparent electrode. The complex transparent electrode of the first electrode may have a different composition from the complex transparent electrode of the second electrode.

Abstract: An anti-reflection structure using surface plasmons and a high-k dielectric material, and a method of manufacturing the anti-reflection structure. The anti-reflection structure may include a high-k dielectric layer formed on a substrate, the high-k dielectric layer configured to allow incident light to pass therethrough, and a nano-material layer on the high-k dielectric layer. The high-k dielectric layer may include at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3) and aluminum oxide (Al2O3).

Abstract: A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer.

Abstract: A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure.

Abstract: A method and apparatus for restoring properties of graphene includes exposing the graphene to plasma having a density in a range from about 0.3*108 cm?3 to about 30*108 cm?3 when the graphene is in a ground state. The method and apparatus may be used for large-area, low-temperature, high-speed, eco-friendly, and silicon treatment of graphene.

Abstract: A photodetector using graphene includes: a gate electrode; a graphene channel layer which is opposite to and spaced apart from the gate electrode and does not have ?-binding; a first electrode which contacts a first side of the graphene channel layer; and a second electrode which contacts a side of the graphene channel layer, where the first and second sides are opposite to each other, and where the graphene channel layer includes a first graphene layer and a first nanoparticle disposed on the first graphene layer. The first graphene layer may include a single graphene layer, or the first graphene layer may include a plurality of single graphene layers, which is sequentially stacked and does not have ?-binding.

Abstract: A photodetector includes a substrate, a graphene layer disposed on the substrate, a first electrode disposed on the graphene layer, and a second electrode disposed on the graphene layer, where the first and second electrodes are spaced apart from each other, and where each of the first and second electrodes comprises a complex transparent electrode. The complex transparent electrode of the first electrode may have a different composition from the complex transparent electrode of the second electrode.

Abstract: Provided are an anti-reflection structure using surface plasmons and a high-k dielectric material, and a method of manufacturing the anti-reflection structure. The anti-reflection structure may include a high-k dielectric layer formed on a substrate, the high-k dielectric layer configured to allow incident light to pass therethrough, and a nano-material layer on the high-k dielectric layer. The high-k dielectric layer may include at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3) and aluminum oxide (Al2O3).

Abstract: A method of producing metallic nanocrystals (107) embedded in high-k dielectric material as well as a nonvolatile flash memory device (100) comprising a discrete charge carrier storage layer, the discrete charge carrier storage layer comprising metallic nanocrystals (107) embedded in high-k dielectric material. In the method described in this invention, firstly an ultra-thin metal film is deposited over a first (105) and a second (106) dielectric layer including high-k dielectric material provided on a substrate (101). Then, the ultra-thin metal film is annealed for forming the metallic nanocrystals (107) on the second dielectric layer (106). Finally, the second dielectric layer (106) and the metallic nanocrystals (107) are covered with a third dielectric layer (108) of high-k dielectric material for forming metallic nanocrystals (107) embedded in high-k dielectric material.

Abstract: A method of producing dielectric oxide nanodots (104) embedded in silicon dioxide as well as a nonvolatile flash memory device comprising a trapping layer (224), the trapping layer (224) comprising dielectric oxide nanodots (104) embedded in silicon dioxide are presented. Firstly an ultra-thin metal film is deposited over a first dielectric layer including silicon dioxide provided on a substrate. Then, the ultra-thin metal film is annealed for forming metallic nanodots (104) on the first dielectric layer. Afterwards, the metallic nanodots (104) are annealed for forming dielectric oxide nanodots (104) on the first dielectric layer. Finally, the first dielectric layer and the dielectric oxide nanodots (104) are covered with a second dielectric layer of silicon dioxide for forming dielectric oxide nanodots (104) embedded in silicon dioxide.

Abstract: A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.

Abstract: A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.

Abstract: A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical.