Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.

Abstract: A display device according to an embodiment includes a display panel and a circuit board connected to the display panel. The circuit board is connected to a bonding area of the display panel by an anisotropic conductive film. The display panel includes a cover insulating layer exposing the bonding area. The cover insulating layer includes at least one trench crossing an edge area, which is located outside the bonding area.

Abstract: A display device according to an embodiment includes a display panel and a circuit board connected to the display panel. The circuit board is connected to a bonding area of the display panel by an anisotropic conductive film. The display panel includes a cover insulating layer exposing the bonding area. The cover insulating layer includes at least one trench crossing an edge area, which is located outside the bonding area.

Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: An oxide thin film transistor (TFT) includes an oxide semiconductor layer including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; an interlayer insulating layer on the gate electrode; and a source electrode and a drain electrode on the interlayer insulating layer and contacting the oxide semiconductor layer, wherein a first reflectance of the first semiconductor layer is greater than a second semiconductor layer.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: Discussed are an antistatic device of a display device, which has a high electrostatic discharge (ESD) speed and reduces consumption power, and a method of manufacturing the same. The antistatic device can include a first switching thin film transistor (TFT) in which an active layer is formed of oxide, a second switching TFT in which an active layer is formed of oxide, and an equalizer TFT in which an active layer is formed of amorphous silicon.

Abstract: A thin film transistor substrate provided with two gate electrodes comprises a thin film transistor including a first gate electrode formed on the substrate; an active layer formed on the first gate electrode; first and second electrodes formed on the active layer; and a second gate electrode formed on the first electrode, the second electrode, and the active layer, wherein the second gate electrode is provided with an opening formed in an area corresponding to at least a part of the second electrode.

Abstract: Discussed are an antistatic device of a display device, which has a high electrostatic discharge (ESD) speed and reduces consumption power, and a method of manufacturing the same. The antistatic device can include a first switching thin film transistor (TFT) in which an active layer is formed of oxide, a second switching TFT in which an active layer is formed of oxide, and an equalizer TFT in which an active layer is formed of amorphous silicon.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: An oxide thin film transistor (TFT) includes an oxide semiconductor layer including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; an interlayer insulating layer on the gate electrode; and a source electrode and a drain electrode on the interlayer insulating layer and contacting the oxide semiconductor layer, wherein a first reflectance of the first semiconductor layer is greater than a second semiconductor layer.

Abstract: A thin film transistor substrate provided with two gate electrodes comprises a thin film transistor including a first gate electrode formed on the substrate; an active layer formed on the first gate electrode; first and second electrodes formed on the active layer; and a second gate electrode formed on the first electrode, the second electrode, and the active layer, wherein the second gate electrode is provided with an opening formed in an area corresponding to at least a part of the second electrode.

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: Disclosed is an LCD device comprising: a substrate; gate and data lines intersecting each other on the substrate; a thin film transistor at the intersection of the gate and data lines; a pixel electrode electrically connected with the thin film transistor; a common electrode forming an electric field with the pixel electrode; and a reflection control layer on at least one of the pixel electrode and common electrode. At this time, at least one electrode of the pixel electrode and common electrode is formed of the opaque metal material, to thereby improve black luminance and contrast ratio. Simultaneously, the reflection control layer is formed on the at least one electrode of the opaque metal material so that it is possible to adjust the reflectivity of external light, and to prevent the problem of rainbow-colored image.

Abstract: There are provided a CMOS image sensor and a method for fabrication thereof. The CMOS image sensor having a reset transistor, a select transistor, a drive transistor and a photodiode, includes an active region in shape of a line, a gate electrode of the drive transistor, which is intersected with the active region, a blocking layer interposed between the active region and the gate electrode in which the blocking layer is formed on an intersection region of the active region and the gate electrode, and a metal contact electrically connected to the gate electrode, wherein the metal contact is not electrically connected to the active region by the blocking layer.

Abstract: A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate.

Abstract: The present invention relates to a copper wire in a semiconductor device in which a barrier layer is formed for improving adhesion of a copper wire without any additional fabricating step; a method for fabricating the same, and a flat panel display device with the same. The copper wire includes a barrier layer formed on an underlying structure, and a copper conductive layer on the barrier layer, wherein the barrier layer includes at least one of a Cu2O layer and a CuOxNy layer.