Abstract: Disclosed are a pulse width modulation (PWM) signal generation circuit and a lamp control system including the same. The PWM signal generation circuit includes a counting circuit configured to generate a counting signal, a pulse period control circuit configured to convert the counting signal into a first analog output signal and compare the first analog output signal with a first comparison voltage to generate a first output signal, a pulse width control circuit configured to convert the counting signal into a second analog output signal and to compare the second analog output signal with a second comparison voltage to generate a second output signal, and a control logic circuit configured to determine a period of a PWM signal based on the first output signal, determine a pulse width of the PWM signal based on the second output signal, and output the PWM signal having the period and the pulse width.

Abstract: Disclosed are a pulse width modulation (PWM) signal generation circuit and a lamp control system including the same. The PWM signal generation circuit includes a pulse period control circuit configured to control charging and discharging of a first capacitor, and generate a first output signal related to a first number of times of charging of the first capacitor, a pulse width control circuit configured to control charging and discharging of a second capacitor, and generate a second output signal related to a second number of times of charging of the second capacitor, and a control logic circuit configured to determine a period of a PWM signal based on the first output signal, determine a pulse width of the PWM signal based on the second output signal, and output the PWM signal having the period and the pulse width.

Abstract: Disclosed is a pulse width modulation signal generation circuit including a charging control circuit connected to and located between a first node connected to a capacitor and a voltage line that supplies an operating voltage, a discharging control circuit connected to and located between the first node and ground, a comparison circuit that generates a comparison signal by comparing a first reference voltage and a second reference voltage with a voltage of the first node, and a control logic circuit that generates a pulse width modulation signal whose level changes based on a level change of the comparison signal and determines a level change timing for the activation of the charging control signal and the discharging control signal using the level change of the comparison signal; and a lamp control system including the pulse width modulation signal generation circuit.

Abstract: The present disclosure relates to an analog-to-digital converter that minimizes or prevents a loss of charges charged in a capacitor array by controlling a switching sequence of switches when switching phases. The analog-to-digital converter includes a DAC circuit including a CDAC circuit and a RDAC circuit, a comparator that compares an output voltage of the DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the DAC circuit and the comparison operation of the comparator in a sampling phase and a comparison phase, outputs digital data based on the comparison result of the comparator, and controls switches that apply the common mode voltage and first and second reference voltages to the capacitor array in the CDAC circuit in response to that the sampling phase is switched to the comparison phase based on a specific switching timing sequence.

Abstract: The present disclosure relates to an analog-to-digital converter that reduces power consumption by reducing an operating current and a semiconductor device having the same. The analog-to-digital converter includes a capacitor-resistor (C-R) hybrid digital-to-analog converter (DAC) circuit including a capacitor digital-to-analog converter (CDAC) circuit including a capacitor array, and a resistor digital-to-analog converter (RDAC) circuit including a resistor string, a comparator that compares an output voltage of the C-R hybrid DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the C-R hybrid DAC circuit and the comparison operation of the comparator using a driving clock with a duty cycle greater than a duty cycle of the first clock based on a system clock, and determines each bit of digital data by receiving the comparison result of the comparator.

Abstract: The present disclosure relates to an oscillator including a charge and discharge circuit which generates a first oscillation signal according to a clock signal using a first constant current and a second oscillation signal according to an inverted clock signal using a second constant current, an integrating circuit which generates a first comparison voltage reflecting an amount of change in the first oscillation signal based on a comparison reference voltage and a second comparison voltage reflecting an amount of change in the second oscillation signal based on the comparison reference voltage, and a comparison circuit which generates the clock signal and the inverted clock signal according to a result of comparison between the first oscillation signal and the first comparison voltage and a result of comparison between the second oscillation signal and the second comparison voltage.

Abstract: Disclosed herein are a frequency generator, which is provided with a frequency automatic correction function and is capable of reducing a frequency test time and a correction time, and a method of correcting a frequency thereof. The frequency generator includes an oscillator configured to generate an output frequency signal according to a frequency control signal, and a frequency corrector configured to generate the frequency control signal for controlling the output frequency of the oscillator using a reference frequency signal.

Abstract: The present disclosure relates to an oscillator including a charge and discharge circuit which generates a first oscillation signal according to a clock signal using a first constant current and a second oscillation signal according to an inverted clock signal using a second constant current, an integrating circuit which generates a first comparison voltage reflecting an amount of change in the first oscillation signal based on a comparison reference voltage and a second comparison voltage reflecting an amount of change in the second oscillation signal based on the comparison reference voltage, and a comparison circuit which generates the clock signal and the inverted clock signal according to a result of comparison between the first oscillation signal and the first comparison voltage and a result of comparison between the second oscillation signal and the second comparison voltage.

Abstract: Disclosed herein are a frequency generator, which is provided with a frequency automatic correction function and is capable of reducing a frequency test time and a correction time, and a method of correcting a frequency thereof. The frequency generator includes an oscillator configured to generate an output frequency signal according to a frequency control signal, and a frequency corrector configured to generate the frequency control signal for controlling the output frequency of the oscillator using a reference frequency signal.

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting higher data rates than a 4th generation (4G) communication system such as long term evolution (LTE). A method for positioning a user equipment (UE) in a wireless communication system includes receiving a reference signal (RS) in a first bandwidth from each of a plurality of anchor nodes scheduled for RS transmission by a network server, determining whether a path overlap has occurred between the UE and the anchor nodes based on symmetry of channel impulse responses of the received RSs, transmitting a bandwidth extension request message to the network server, upon occurrence of a path overlap, receiving an RS in a second bandwidth larger than the first bandwidth from each of the plurality of anchor nodes in response to the transmission of the bandwidth extension request message, and generating information required to position the UE, using the RSs received in the second bandwidth.

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting higher data rates than a 4th generation (4G) communication system such as long term evolution (LTE). A method for positioning a user equipment (UE) in a wireless communication system includes receiving a reference signal (RS) in a first bandwidth from each of a plurality of anchor nodes scheduled for RS transmission by a network server, determining whether a path overlap has occurred between the UE and the anchor nodes based on symmetry of channel impulse responses of the received RSs, transmitting a bandwidth extension request message to the network server, upon occurrence of a path overlap, receiving an RS in a second bandwidth larger than the first bandwidth from each of the plurality of anchor nodes in response to the transmission of the bandwidth extension request message, and generating information required to position the UE, using the RSs received in the second bandwidth.

Abstract: The present disclosure provides a method for performing a cellular communication in a device-to-device communication system, the method comprising the operations of: receiving scheduling to transmit an uplink signal through a specific resource of a discovery channel from a base station; generating uplink scheduling information notifying scheduling of the uplink signal; and transmitting the uplink scheduling information through at least one discovery resource of the discovery channel.

Abstract: The present disclosure provides a method for performing a cellular communication in a device-to-device communication system, the method comprising the operations of: receiving scheduling to transmit an uplink signal through a specific resource of a discovery channel from a base station; generating uplink scheduling information notifying scheduling of the uplink signal; and transmitting the uplink scheduling information through at least one discovery resource of the discovery channel.