Patents by Inventor Won-Jun Lee

Won-Jun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050023634
    Abstract: Provided is a method of fabricating a shallow trench isolation (STI) structure having a high aspect ratio and improved insulating properties. The exemplary method includes filling a shallow trench isolation region opening with an undoped polysilicon layer, removing an upper portion of the undoped polysilicon layer to form a second opening having a reduced aspect ratio relative to the original opening and filling the second opening with an insulating material to complete the STI structure. Additional protective layers including silicon oxide, silicon nitride and/or a capping layer may be provided on the sidewalls of the opening before depositing the undoped polysilicon.
    Type: Application
    Filed: June 8, 2004
    Publication date: February 3, 2005
    Inventors: Byoung-Moon Yoon, Min-Jin Lee, Yong-Sun Ko, In-Seak Hwang, Won-Jun Lee
  • Publication number: 20050026452
    Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. An etchant or chemical solution is applied to the dielectric layer and bubbles in the etchant are prevented from adhering to the electrode. In one embodiment, prior to etching, the protruding portion is covered with a buffer layer to prevent bubbles in the etchant from adhering to the electrode. Thus, the etchant can etch the dielectric layers without being blocked by bubbles included therein.
    Type: Application
    Filed: May 26, 2004
    Publication date: February 3, 2005
    Inventors: Won-Jun Lee, Byoung-Moon Yoon, In-Seak Hwang, Yong-Sun Ko
  • Publication number: 20040262761
    Abstract: A metal thin film of a semiconductor device and method for forming the same is disclosed, in which excellent step coverage and surface roughness are maintained. The metal thin film of a semiconductor device according to the present invention includes: a barrier metal layer formed on a semiconductor substrate; and a PVD seed thin film, a CVD thin film, and a PVD reflow thin film sequentially formed on the barrier metal layer, wherein the PVD seed thin film, the CVD thin film and the PVD reflow thin film are of the same material.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 30, 2004
    Applicant: Hynix Semiconductor Inc.
    Inventor: Won Jun Lee
  • Patent number: 6780752
    Abstract: A metal thin film of a semiconductor device and method for forming the same is disclosed, in which excellent step coverage and surface roughness are maintained. The metal thin film of a semiconductor device according to the present invention includes: a barrier metal layer formed on a semiconductor substrate; and a PVD seed thin film, a CVD thin film, and a PVD reflow thin sequentially formed on the barrier metal layer, wherein the PVD seed thin film, the CVD thin film and the PVD reflow thin film are of the same material.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: August 24, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Jun Lee
  • Publication number: 20030227045
    Abstract: Methods of forming an electronic structure can include forming an interlayer insulating layer on a substrate, and forming a storage node comprising a base and sidewalls extending away from the base. The interlayer insulating layer can have a contact hole therein exposing a portion of the substrate. Moreover, the storage node base can be in the contact hole and the sidewalls can extend away from the base and away from the substrate with portions of the sidewalls being within the contact hole and with portions of the sidewalls extending outside the contact hole beyond the interlayer insulating layer away from the substrate. Related structures are also discussed.
    Type: Application
    Filed: May 27, 2003
    Publication date: December 11, 2003
    Inventors: Won-Jun Lee, In-Seak Hwang, Ji-Chul Shin
  • Publication number: 20030186498
    Abstract: A method for forming a multilayer metal thin film capable of improving electromigration reliability. The method includes steps of forming a Ti film having an <002> crystal orientation by using an ionized physical vapor deposition method, forming a TiN film on the Ti film in order to form a multilayer stack, wherein the TiN film has an <111> crystal orientation, and forming an aluminum film on the multilayer stack in an <111> crystal orientation. Accordingly, the aluminum metal interconnection increases the <002> orientation of the Ti film and improves the <111> orientation of the aluminum to control electromigration resistance, by using the IPVD method in forming the Ti film as an underlayer of the aluminum film.
    Type: Application
    Filed: March 26, 2003
    Publication date: October 2, 2003
    Applicant: HYUNDAI ELECTRONICS INDUSTRIES CO., INC.
    Inventor: Won-Jun Lee
  • Publication number: 20030106575
    Abstract: A wafer guide for supporting at least one semiconductor wafer during a cleaning process, includes side panels having a plurality of side fixing grooves on an upper surface thereof for stabilizing the at least one semiconductor wafer and for maintaining a sufficient distance between a surface of the at least one semiconductor wafer and an adjacent surface; a center panel having a plurality of center fixing grooves on the upper surface thereof for supporting the at least one semiconductor wafer, each of the plurality of center fixing grooves having inner walls, wherein a contact line is formed on each of the inner walls of the center fixing grooves, and wherein the center panel is positioned between the pair of side panels; and a pair of fixing plates, one of the pair of fixing plates being fixedly attached at each end of the center panel and the pair of side panels.
    Type: Application
    Filed: November 15, 2002
    Publication date: June 12, 2003
    Inventors: Bong-Ho Moon, Yong-Sun Ko, Won-Jun Lee, Yong-Myung Jun, In-Seak Hwang
  • Patent number: 6451663
    Abstract: A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: September 17, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Gil Choi, Tae Hyuk Ahn, Sang Sup Jeong, Dae Hyuk Chung, Won Jun Lee
  • Publication number: 20020052089
    Abstract: A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.
    Type: Application
    Filed: October 24, 2001
    Publication date: May 2, 2002
    Inventors: Sung-Gil Choi, Tae Hyuk Ahn, Sang Sup Jeong, Dae Hyuk Chung, Won Jun Lee
  • Publication number: 20020001946
    Abstract: A method for forming a multilayer metal thin film capable of improving electromigration reliability. The method includes steps of forming a Ti film having an <002> crystal orientation by using an ionized physical vapor deposition method, forming a TiN film on the Ti film in order to form a multilayer stack, wherein the TiN film has an <111> crystal orientation, and forming an aluminum film on the multilayer stack in an <111> crystal orientation. Accordingly, the aluminum metal interconnection increases the <002> orientation of the Ti film and improves the <111> orientation of the aluminum to control electromigration resistance, by using the IPVD method in forming the Ti film as an underlayer of the aluminum film.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 3, 2002
    Inventor: Won-Jun Lee
  • Patent number: 6242340
    Abstract: A method of forming an interconnection layer in a semiconductor device is provided that improves the mass productivity and the reliability of the interconnection by forming a sidewall spacer on the sidewalls of a trench that is formed in an insulation film having a low dielectric constant. The sidewall spacer maintains the sidewall profile of the trench during subsequent processing steps.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: June 5, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Won-Jun Lee
  • Patent number: 5817367
    Abstract: A method of forming a thin film of copper on a substrate includes a first step of conducting a chemical vapor deposition (CVD) process using a metal organic (MO) source while applying a first bias voltage to the surface of the substrate and a second step of conducting a chemical vapor deposition process using a metal organic source while applying a second bias voltage to the substrate, wherein the second bias voltage is opposite in polarity to the first bias voltage. The process may include a third step of conducting a chemical vapor deposition process using a metal organic source while applying a third bias voltage to the substrate, where the third bias voltage has the same polarity as the first bias voltage.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: October 6, 1998
    Assignee: LG Semicon., Ltd.
    Inventors: Soung Soon Chun, Chong Ook Park, Dong Won Kim, Won Jun Lee, Sa Kyun Rha, Kyung Il Lee