Abstract: A non-linear digital-to-analog converter is disclosed, which realizes non-linear output with overlapped resistor string. The non-linear digital-to-analog converter includes a first reference voltage select switching portion for selectively outputting first and second reference voltages Vh1 and Vc1 from externally applied reference voltages Vref[1, . . . 2N/2] and third and fourth reference voltages Vh2 and Vc2 from externally applied reference voltages Vref[0, . . . 2N/2−1] if N bit digital value is input, a resistor string block for outputting Vh[0, . . . 2N/2−1] number of level voltages, Vc[0, . . . 2N/2−1] number of level voltages, and V1[0, . . . 2N/2−1] number of level voltages from any one of the reference voltages Vh1 and Vc1 and any one of the reference voltages Vh2 and Vc2, a second reference voltage select switching portion for outputting a first analog conversion voltage V1 from the Vh[0, . . .

Abstract: The present invention discloses a multiplexer including that provides an output signal having a voltage range substantially equal to an input signal. The multiplexer further provides a breakdown prevention device that protects elements connected to an output terminal. The multiplexer can be used in an LCD driver or the like. The multiplexer according to the present invention can include a first switching circuit that receives a first input signal, a second switching circuit that receives a second input signal, wherein the first and second switching circuits are complementarily enabled in response to a three control signals, a third switching circuit that receives the first input signal switched from the first switching circuit and a fourth switching circuit that receives the second input signal switched from the second switching circuit. The third and fourth switching circuits are complementarily enabled by a selection signal to provide one of the first and second input signals to the output terminal.

Abstract: A CMOS (Complementary Metal Oxide Semiconductor) digital level shift circuit converts a first source voltage which ranges from Vcc to the ground, into a second source voltage which ranges from Vdd to the ground. The circuit includes an inverter and a latch circuit. The latch circuit includes a latch unit and a voltage distributor having a plurality of PMOS and NMOS transistors. The plurality of MOS transistors are serially connected in the voltage distributor, whereby the second source voltage which is higher than the channel breakdown voltages of the respective MOS transistors, is externally output.

Abstract: A high-output voltage generating circuit that prevents transistor breakdown includes first and second switching circuits coupled to each other at a first common gate, the first common gate being connected to a first control signal, and the first and second switching circuits being connected to a common input signal; third and fourth switching circuits coupled to each other at a second common gate, the second common gate being connected to a second control signal; a signal output unit having first and second transistors coupled to each other at a third common gate, the third common gate being connected to the second control signal; a third transistor, coupled to a first voltage, receiving a first signal at a gate from the first switching circuit; a fourth transistor, coupled to the third transistor, receiving a second signal from the third switching circuit at a gate, the fourth transistor being coupled to the first transistor of the signal output unit; a fifth transistor, coupled to the second transistor of t