Abstract: Proposed is a wireless data transmission method including: receiving, by a transmitter, a display signal on the basis of a control signal; extracting required data from the received display signal; converting the display signal into an extremely-high frequency RF signal on the basis of the required data; transmitting and/or receiving the extremely-high frequency RF signal; and converting, in a receiver, the received extremely-high frequency RF signal into the display signal.

Abstract: Proposed is a wireless data transmission method including: receiving, by a transmitter on the basis of a control signal, a first display signal having a first interface; extracting required data from the received display signal; converting the first display signal into an extremely-high frequency RF signal on the basis of the required data; transmitting and/or receiving the extremely-high frequency RF signal; and converting, in a receiver, the received extremely-high frequency RF signal into a second display signal having a second interface. The wireless data transmitter and receiver may use different communication protocols, and the transmitter and the receiver may include an operation of detecting the communication protocols that a counterpart receiver and transmitter use and performing conversion into the protocols for transmission or reception.

Abstract: Proposed is a wireless data transmission method including: detecting an interface of a control signal received from an external device; converting, on the basis of the detected interface, the control signal into a second PP signal having a second frequency band; transmitting and/or receiving the second RF signal; reconverting the second RF signal into the control signal; converting, in a transmitter on the basis of the control signal, a display signal into a first RF signal having a first frequency band distinct from the second frequency band; transmitting and/or receiving the first RF signal; and converting, in a receiver, the received first RF signal into the display signal.

Abstract: An electronic device comprising a semiconductor memory including a plurality of memory cells is provided. Each of the plurality of memory cells includes: a first electrode layer; a variable resistance layer disposed over the first electrode layer; a second electrode layer disposed over the variable resistance layer; and an interface electrode layer interposed between the first electrode layer and the variable resistance layer or between the second electrode layer and the variable resistance layer. The interface electrode layer includes a porous metal-containing layer.

Abstract: A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.

Abstract: A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.

Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.

Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.