Patents by Inventor Won-kyung Chung

Won-kyung Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220207141
    Abstract: An apparatus for generating a signature that reflects the similarity of a malware detection and classification system of the present invention includes a pre-processing unit configured to generate an input vector from input information, a classification unit configured to calculate a latent vector which indicates the similarity between at least one malware classification and the input vector by performing a plurality of computations to which learned weights of a plurality of layers are applied on the input vector through a deep neural network model, and a signature generation unit configured to generate a signature of the malware in a form of a binary vector by quantizing the latent vector.
    Type: Application
    Filed: December 30, 2021
    Publication date: June 30, 2022
    Inventors: Ui Jung CHUNG, Won Kyung LEE, Hyeong Jin BYEON
  • Publication number: 20220148648
    Abstract: A memory apparatus may include a row hammer control circuit, The row hammer control circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The row hammer apparatus may set a threshold value for performing a refresh operation, as one of a plurality of values, based on the plurality of selection control signals.
    Type: Application
    Filed: April 7, 2021
    Publication date: May 12, 2022
    Applicant: SK hynix Inc.
    Inventor: Won Kyung CHUNG
  • Patent number: 10636460
    Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Won Kyung Chung
  • Publication number: 20190341087
    Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.
    Type: Application
    Filed: September 27, 2018
    Publication date: November 7, 2019
    Applicant: SK hynix Inc.
    Inventors: Seung Hun LEE, Won Kyung CHUNG
  • Patent number: 10133284
    Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Won Kyung Chung
  • Patent number: 10008252
    Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 26, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Tae-Jin Kang, Hyun-Seung Kim, Nam-Kyu Jang, Won-Seok Choi, Won-Kyung Chung, Seung-Hun Lee
  • Publication number: 20180061472
    Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.
    Type: Application
    Filed: April 3, 2017
    Publication date: March 1, 2018
    Inventors: Sang-Ah HYUN, Tae-Jin KANG, Hyun-Seung KIM, Nam-Kyu JANG, Won-Seok CHOI, Won-Kyung CHUNG, Seung-Hun LEE
  • Publication number: 20170364108
    Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Applicant: SK hynix Inc.
    Inventors: Seung Hun LEE, Won Kyung CHUNG
  • Patent number: 9785158
    Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 10, 2017
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Won Kyung Chung
  • Patent number: 9673814
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Won Kyung Chung, Saeng Hwan Kim
  • Publication number: 20170075367
    Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
    Type: Application
    Filed: February 11, 2016
    Publication date: March 16, 2017
    Inventors: Seung Hun LEE, Won Kyung CHUNG
  • Patent number: 9584124
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 28, 2017
    Assignee: SK hynix Inc.
    Inventors: Won Kyung Chung, Saeng Hwan Kim
  • Publication number: 20170033791
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.
    Type: Application
    Filed: November 12, 2015
    Publication date: February 2, 2017
    Inventors: Won Kyung CHUNG, Saeng Hwan KIM
  • Publication number: 20160373113
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Application
    Filed: August 31, 2016
    Publication date: December 22, 2016
    Inventors: Won Kyung CHUNG, Saeng Hwan KIM
  • Patent number: 9466349
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller generates a clock signal and updates external count signals in response to an external update signal. The semiconductor device generates count signals by counting pulses of a strobe signal during a period when a section signal is in an active state. The section signal is generated in response to a first control signal including pulses that are periodically generated. The semiconductor device also generates the external update signal and the external count signals if a combination of the count signals is changed.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 11, 2016
    Assignee: SK HYNIX INC.
    Inventor: Won Kyung Chung
  • Patent number: 9461647
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 4, 2016
    Assignee: SK HYNIX INC.
    Inventors: Won Kyung Chung, Saeng Hwan Kim
  • Publication number: 20160164521
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Application
    Filed: March 4, 2015
    Publication date: June 9, 2016
    Inventors: Won Kyung CHUNG, Saeng Hwan KIM
  • Patent number: 8278967
    Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 2, 2012
    Assignee: SK Hynix Inc.
    Inventor: Won Kyung Chung
  • Patent number: 8169846
    Abstract: A refresh control circuit of a semiconductor memory apparatus includes: a variable oscillator configured to generate a room-temperature oscillation signal and a limit-temperature oscillation signal in response to a temperature state signal; a cycle selector configured to selectively output the room temperature oscillation signal and the limit-temperature oscillation signal as a variable oscillation signal in response to the temperature state signal; a refresh signal generator configured to generate a refresh signal in response to the variable oscillation signal and a fixed oscillation signal; and a temperature state detector configured to generate the temperature state signal by detecting current temperature in response to the room-temperature oscillation signal and the fixed oscillation signal.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Kyung Chung
  • Publication number: 20110089964
    Abstract: Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.
    Type: Application
    Filed: December 29, 2010
    Publication date: April 21, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hun SEO, Won-kyung Chung, Han-na Park