Abstract: A method for operating a memory includes: activating a row which is selected based on a row address among a plurality of rows; receiving a counting command while the selected row is activated; reading a number of accesses from memory cells of particular columns of the selected row in response to the counting command; increasing the number of accesses; and writing the increased number of accesses into the memory cells of the particular columns of the selected row.

Abstract: A memory apparatus may include a row hammer control circuit. The row hammer control circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The row hammer apparatus may set a threshold value for performing a refresh operation, as one of a plurality of values, based on the plurality of selection control signals.

Abstract: A memory apparatus may include a row hammer control circuit, The row hammer control circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The row hammer apparatus may set a threshold value for performing a refresh operation, as one of a plurality of values, based on the plurality of selection control signals.

Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.

Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller generates a clock signal and updates external count signals in response to an external update signal. The semiconductor device generates count signals by counting pulses of a strobe signal during a period when a section signal is in an active state. The section signal is generated in response to a first control signal including pulses that are periodically generated. The semiconductor device also generates the external update signal and the external count signals if a combination of the count signals is changed.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.

Abstract: A refresh control circuit of a semiconductor memory apparatus includes: a variable oscillator configured to generate a room-temperature oscillation signal and a limit-temperature oscillation signal in response to a temperature state signal; a cycle selector configured to selectively output the room temperature oscillation signal and the limit-temperature oscillation signal as a variable oscillation signal in response to the temperature state signal; a refresh signal generator configured to generate a refresh signal in response to the variable oscillation signal and a fixed oscillation signal; and a temperature state detector configured to generate the temperature state signal by detecting current temperature in response to the room-temperature oscillation signal and the fixed oscillation signal.