Patents by Inventor Won-Mo Park
Won-Mo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110049670Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.Type: ApplicationFiled: July 21, 2010Publication date: March 3, 2011Inventors: Ho-Ju Song, Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim
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Publication number: 20100187101Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, lower electrodes having cylindrical shapes are provided to be arranged repeatedly on a substrate. Upper surfaces of the lower electrodes are flat so that the lower electrodes have uniform heights. Supporting structures are provided between the lower electrodes to support the lower electrode, the supporting structure partially contacting outer surfaces of sidewalls of the lower electrodes that are arranged in a line. A dielectric layer is formed on surfaces of the lower electrodes and the supporting structures. An upper electrode is provided on the dielectric layer. The semiconductor device includes a capacitor having an improved capacitance. Further, the capacitor includes the support structure between the lower electrodes to prevent the adjacent lower electrodes from being short each other.Type: ApplicationFiled: January 22, 2010Publication date: July 29, 2010Inventors: Gil-Sub Kim, Won-Mo Park, Seong-Ho Kim, Dong-Kwan Yang, Ho-Ju Song
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Publication number: 20100187588Abstract: Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.Type: ApplicationFiled: August 7, 2009Publication date: July 29, 2010Inventors: Gil-Sub KIM, Won Mo PARK, Seong Ho KIM, Dong Kwan YANG
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Publication number: 20100120212Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.Type: ApplicationFiled: November 6, 2009Publication date: May 13, 2010Inventors: Dong-kwan Yang, Seong-ho Kim, Won-mo Park, Gil-sub Kim
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Patent number: 7564135Abstract: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.Type: GrantFiled: May 24, 2006Date of Patent: July 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Won-Mo Park
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Patent number: 7393742Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically connected to the contact plug and formed on the insulating layer and the contact plug, an etching stopping layer formed on the buffer conductive layer pattern, a gap between the buffer conductive layer pattern and the etching stopping layer, a capacitor lower electrode electrically connected to the buffer conductive layer pattern and formed on the buffer conductive layer pattern. The gap is filled by a portion of the capacitor lower electrode.Type: GrantFiled: February 17, 2006Date of Patent: July 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Won-Mo Park
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Patent number: 7323746Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.Type: GrantFiled: September 14, 2005Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Mo Park, Jae-Choel Paik, Du-Heon Song, Dong-Hyun Kim, Chang-Sub Lee
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Publication number: 20070170486Abstract: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.Type: ApplicationFiled: May 24, 2006Publication date: July 26, 2007Inventor: Won-Mo PARK
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Publication number: 20060255391Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: July 24, 2006Publication date: November 16, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Beom KIM, Won-Mo PARK, Yun-Jae LEE, Joon-Mo KWON, Myoung-Hee HAN, Man-Jong YU
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Patent number: 7101769Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: GrantFiled: February 10, 2004Date of Patent: September 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Publication number: 20060186453Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically connected to the contact plug and formed on the insulating layer and the contact plug, an etching stopping layer formed on the buffer conductive layer pattern, a gap between the buffer conductive layer pattern and the etching stopping layer, a capacitor lower electrode electrically connected to the buffer conductive layer pattern and formed on the buffer conductive layer pattern. The gap is filled by a portion of the capacitor lower electrode.Type: ApplicationFiled: February 17, 2006Publication date: August 24, 2006Inventor: Won-Mo Park
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Publication number: 20060060936Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.Type: ApplicationFiled: September 14, 2005Publication date: March 23, 2006Inventors: Won-Mo Park, Jae-Choel Paik, Du-Heon Song, Dong-Hyun Kim, Chang-Sub Lee
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Publication number: 20040159909Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Patent number: 6498044Abstract: A capacitor having a perovskite series dielectric film, and manufacturing method thereof are provided. The perovskite series dielectric film capacitor is characterized in that the perovskite series dielectric film contains copper. The method of manufacturing the perovskite series dielectric film which contains copper includes forming the perovskite series dielectric film on a lower electrode, forming a CuXO film on the perovskite series dielectric film, and permitting CuXO or copper of the CuXO film to penetrate the perovskite series dielectric film preferably by a heat treatment. In the perovskite series dielectric film capacitor, CuXO or copper penetrates the grain boundary of the perovskite series dielectric film having a columnar crystal structure, thereby improving a leakage current characteristic of the perovskite series dielectric film.Type: GrantFiled: October 30, 2000Date of Patent: December 24, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Won-mo Park
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Patent number: 5965939Abstract: A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.Type: GrantFiled: April 22, 1997Date of Patent: October 12, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Kyeong-tae Kim, Yun-seung Shin, Young-hun Park, Won-mo Park, Ji-hong Ahn
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Patent number: 5700709Abstract: A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.Type: GrantFiled: October 25, 1995Date of Patent: December 23, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Jong-jin Lee
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Patent number: 5591670Abstract: A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.Type: GrantFiled: June 5, 1995Date of Patent: January 7, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Jung-hyun Shin, Young-hun Park
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Patent number: 5502336Abstract: A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.Type: GrantFiled: March 14, 1994Date of Patent: March 26, 1996Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Jung-hyun Shin, Young-hun Park
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Patent number: 5488007Abstract: A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.Type: GrantFiled: April 16, 1993Date of Patent: January 30, 1996Assignee: Samsung Electronics Co., Ltd.Inventors: Kyeong-Tae Kim, Yun-seung Shin, Young-hun Park, Won-mo Park, Ji-hong Ahn
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Patent number: 5443993Abstract: A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.Type: GrantFiled: November 23, 1994Date of Patent: August 22, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Jong-jin Lee