Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: An ultrasonic probe that acquires an ultrasonic image to diagnose or treat an object, and an ultrasonic imaging apparatus including the same, wherein the ultrasonic probe includes a case, a transducer disposed inside the case to generate ultrasonic waves, a biopsy needle inserted into an object in the vicinity of the case, and a sensor unit including a sensor provided to measure a position of the biopsy needle and disposed inside the transducer, wherein the transducer includes a piezoelectric layer configured to generate ultrasonic waves, a sound absorbing layer disposed on one side of the piezoelectric layer to absorb the ultrasonic waves generated from the piezoelectric layer, and a sound absorbing member disposed on one side of the sound absorbing layer, and the sensor unit is disposed inside the sound absorbing member.

Abstract: An image sensing device includes first and anterior comparators and first and second posterior comparators. The first anterior comparator generates a first anterior comparison signal based on a first pixel signal and a ramp signal. The first posterior comparator performs a first comparison that compares the first anterior comparison signal with a first reference signal under a first comparison precondition and generates a first posterior comparison signal corresponding to a result of the first comparison. The second anterior comparator generates a second anterior comparison signal based on a second pixel signal and the ramp signal. The second posterior comparator performs a second comparison that compares the second anterior comparison signal with a second reference signal under a second comparison precondition different from the first comparison precondition. The second posterior comparator generates a second posterior comparison signal corresponding to a result of the second comparison.

Abstract: An image sensing device includes first and anterior comparators and first and second posterior comparators. The first anterior comparator generates a first anterior comparison signal based on a first pixel signal and a ramp signal. The first posterior comparator performs a first comparison that compares the first anterior comparison signal with a first reference signal under a first comparison precondition and generates a first posterior comparison signal corresponding to a result of the first comparison. The second anterior comparator generates a second anterior comparison signal based on a second pixel signal and the ramp signal. The second posterior comparator performs a second comparison that compares the second anterior comparison signal with a second reference signal under a second comparison precondition different from the first comparison precondition. The second posterior comparator generates a second posterior comparison signal corresponding to a result of the second comparison.

Abstract: An image sensing device includes a pixel array; a plurality of lines coupled to the pixel array; a readout circuit coupled to the plurality of lines and structured to output a readout reset signal and a readout data; first readout lines coupled to the readout circuit and structured to transfer readout reset signals and readout data signals; a global counter coupled to count the readout reset signals and the readout data signals; a first storing circuit coupled to the first readout lines to receive the readout reset signals and the readout data signals; a line control circuit coupled to the first storing circuit; second readout lines coupled to the line control circuit and structured to transfer the readout control signals received from the line control circuit; and a second storing circuit coupled to the second readout lines to receive the readout control signals.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: An image sensing device includes a pixel array; a plurality of lines coupled to the pixel array; a readout circuit coupled to the plurality of lines and structured to output a readout reset signal and a readout data; first readout lines coupled to the readout circuit and structured to transfer readout reset signals and readout data signals; a global counter coupled to count the readout reset signals and the readout data signals; a first storing circuit coupled to the first readout lines to receive the readout reset signals and the readout data signals; a line control circuit coupled to the first storing circuit; second readout lines coupled to the line control circuit and structured to transfer the readout control signals received from the line control circuit; and a second storing circuit coupled to the second readout lines to receive the readout control signals.

Abstract: Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Abstract: A count circuit includes a count block suitable for generating count code signals for a predetermined count period including a first period and a second period; and a storage block suitable for storing first bit signals among a plurality of bit signals included in the count code signals, for the first period, and storing remaining bit signals among the plurality of bit signals for the second period.

Abstract: An item recommendation method and apparatus are provided. The item recommendation method and apparatus may recognize items preferred before a user uses items, based on items rated by the user, and may recommend an item to the user based on preferences for the recognized items.

Abstract: A group selection circuit includes an input block suitable for receiving a last column select signal of a previous column switch group and a last column select signal of a current column switch group; and a group selection block suitable for generating a group select signal that is activated from a first edge of the last column select signal of the previous column switch group to a first edge of the last column select signal of the current column switch group, in response to an output signal of the input block.

Abstract: Disclosed are a latch circuit receiving a negative output of a next latch stage circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a form of a ring. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current latch stage receives an output of a preceding latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Abstract: A count circuit includes a count block suitable for generating count code signals for a predetermined count period including a first period and a second period; and a storage block suitable for storing first bit signals among a plurality of bit signals included in the count code signals, for the first period, and storing remaining bit signals among the plurality of bit signals for the second period.

Abstract: A counting apparatus that includes a global counting unit suitable for performing a counting operation by controlling a counting bit number based on a count masking signal; a one-shot pulse generation unit suitable for generating a storage instruction signal based on the count masking signal; a latch unit suitable for storing a counting value outputted from the global counting unit based on the storage instruction signal; and a storage unit suitable for storing the counting value loaded from the latch unit.

Abstract: A group selection circuit includes an input block suitable for receiving a last column select signal of a previous column switch group and a last column select signal of a current column switch group; and a group selection block suitable for generating a group select signal that is activated from a first edge of the last column select signal of the previous column switch group to a first edge of the last column select signal of the current column switch group, in response to an output signal of the input block.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.

Abstract: An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.