Patents by Inventor Won-Seong Lee
Won-Seong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140195Abstract: The present disclosure relates to a transmission of an agricultural work vehicle, the transmission comprising: a pre-shift part for performing speed shifting on driving transmitted from an engine of an agricultural work vehicle; a clutch part connected to the pre-shift part so as to selectively output driving transmitted from the pre-shift part; an adjusting part connected to the clutch part so as to perform speed shifting on driving transmitted from the clutch part; and a subsequent shift part connected to the adjusting part so as to perform speed shifting on driving transmitted from the adjusting part.Type: ApplicationFiled: December 21, 2023Publication date: May 2, 2024Inventors: Jung Su HAN, Ki Taeg LEE, Won Woo PARK, Ji Hun YU, Taek Seong KIM, Young-Gyu LEE
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Patent number: 11922624Abstract: An apparatus for providing brain lesion information based on an image includes a magnetic resonance angiography (MRA) provider configured to provide an environment capable of displaying 3D time-of-flight magnetic resonance angiography (3D TOF MRA) using user input, a brain lesion input unit configured to generate and manage a brain lesion image, a maximum intensity projection (MIP) converter configured to configure MIP image data including at least one image frame corresponding to a projection position of the brain lesion image, a noise remover configured to remove noise of brain lesion information and to configure corrected MIP image data, from which the noise is removed, and an MRA reconfiguration unit configured to reconfigure a corrected brain lesion image by back-projecting the corrected MIP image data.Type: GrantFiled: December 27, 2019Date of Patent: March 5, 2024Assignee: JLK INC.Inventors: Won Tae Kim, Shin Uk Kang, Myung Jae Lee, Dong Min Kim, Jin Seong Jang
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Patent number: 7517762Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.Type: GrantFiled: May 26, 2005Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
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Publication number: 20050221539Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.Type: ApplicationFiled: May 26, 2005Publication date: October 6, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
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Patent number: 6913953Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.Type: GrantFiled: December 31, 2002Date of Patent: July 5, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
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Patent number: 6844240Abstract: A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.Type: GrantFiled: September 10, 2001Date of Patent: January 18, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Young-woo Park, Yong-chul Oh, Won-Seong Lee
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Patent number: 6607983Abstract: The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.Type: GrantFiled: November 6, 2000Date of Patent: August 19, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Youl Chun, Yun-Jae Lee, Won-Seong Lee, Jeong-Hoon Oh, Kyu-Hyun Lee
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Publication number: 20030134457Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.Type: ApplicationFiled: December 31, 2002Publication date: July 17, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
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Patent number: 6525398Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.Type: GrantFiled: August 29, 2000Date of Patent: February 25, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
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Publication number: 20020137279Abstract: A method and structure of forming an trench isolation is provided which protects a nitride liner in the trench during subsequent plasma processing by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. The method includes the steps of forming a trench mask on a semiconductor substrate to define a trench forming region, etching the semiconductor substrate using the trench mask and forming a trench therein, forming a thermal oxide layer on a bottom and sidewalls of the trench so as to remove substrate damage caused by the step of etching the semiconductor substrate, forming a material layer on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized, forming a protection layer on the oxidation barrier layer, plasma processing the bottom and sidewalls of the trench, and filling up the trench with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.Type: ApplicationFiled: September 10, 2001Publication date: September 26, 2002Inventors: Young-Woo Park, Yong-Chul Oh, Won-Seong Lee
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Patent number: 6399476Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.Type: GrantFiled: November 2, 1999Date of Patent: June 4, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Yang Kim, Si-Woo Lee, Won Seong Lee, Sang-Pil Sim
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Patent number: 6326282Abstract: A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.Type: GrantFiled: April 14, 1999Date of Patent: December 4, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Young-woo Park, Yong-chul Oh, Won-Seong Lee
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Patent number: 6121146Abstract: A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer.Type: GrantFiled: June 5, 1998Date of Patent: September 19, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Un Yoon, In-Kwon Jeong, Won-Seong Lee
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Patent number: 5858833Abstract: Integrated circuit memory devices are manufactured by forming spaced apart source and drain regions in an integrated circuit substrate, and an insulated gate on the integrated circuit substrate therebetween. An interlayer insulating layer is formed on the integrated circuit substrate, including first and second conductive pad contacts which extend therethrough and which electrically contact the source and the drain region, respectively. A trench is formed in the interlayer insulating layer, including in the second conductive pad contact. A first insulating layer is formed to line the trench, except for adjacent the second conductive pad contact. A buried bit line is formed in the trench, electrically contacting the second conductive pad contact through the first insulating layer. A second insulating layer is formed on the first insulating layer and on the buried bit line, except for adjacent the first conductive pad contact.Type: GrantFiled: January 21, 1997Date of Patent: January 12, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Won-seong Lee, Chang-gyu Hwang
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Patent number: 5728627Abstract: A conductive planarization layer, preferably a doped polysilicon layer, is used as a planarization layer for forming a conductive interconnect, such as a memory device bit line, thereon. Etching of the doped polysilicon planarization layer may be accurately controlled to form a planarized layer of controlled thickness, without requiring high temperature reflow heating of boro-phospo-silicate glass which can degrade transistor parameters. In particular, an insulating layer is formed on spaced apart source and drain regions and on the gate therebetween. A doped polysilicon layer is formed on the insulating layer. The doped polysilicon layer is planarized. A contact hole is formed in the insulating layer and in the doped polysilicon layer, to thereby expose the source or drain region. A conductive interconnect is then formed in the contact hole and on the gate.Type: GrantFiled: November 14, 1996Date of Patent: March 17, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: In-ho Nam, Won-seong Lee