Abstract: Disclosed are a display panel, which is capable of reducing mura at low grayscale, and a method of manufacturing the same. The thickness of a gate insulating layer of a driving thin-film transistor is increased, and the mobility of the driving thin-film transistor is reduced to reduce the K-factor of the driving thin-film transistor. The display panel includes a plurality of sub-pixels, each having a driving thin-film transistor, a switching thin-film transistor, and a storage capacitor on a substrate. The driving thin-film transistor includes a semiconductor layer comprising a source region and a drain region; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode electrically connected to the source region and the drain region; and a gate insulating layer located between the semiconductor layer and the gate electrode. The semiconductor layer is a dehydrogenated semiconductor layer.

Abstract: Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in a surface of the substrate adjacent to the trench region and in contact with the channel region, and gate electrodes at sides of the trench insulated from the trench wall.

Abstract: Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in a surface of the substrate adjacent to the trench region and in contact with the channel region, and gate electrodes at sides of the trench insulated from the trench wall.

Abstract: Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in a surface of the substrate adjacent to the trench region and in contact with the channel region, and gate electrodes at sides of the trench insulated from the trench wall.