Patents by Inventor Won-sok Lee
Won-sok Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230147083Abstract: A semiconductor memory device includes a cell area and a peripheral area, a base insulating layer including opposed first front and rear surfaces in the cell area, a first semiconductor substrate including opposed second front and rear surfaces in the peripheral area, an active pattern on the first front surface, a first conductive line extending in a first direction on a side of the active pattern, a capacitor structure on the active pattern, a first circuit element on the second front surface, and a second conductive line extending in a second direction intersecting the first direction on the first rear surface and the second rear surface. The active pattern extends in a vertical direction intersecting the first direction and the second direction to electrically connect the second conductive line to the capacitor structure.Type: ApplicationFiled: June 22, 2022Publication date: May 11, 2023Inventors: Min Hee Cho, Dong Il Bae, Won Sok Lee, Yong Seok Kim
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Publication number: 20220223732Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.Type: ApplicationFiled: August 12, 2021Publication date: July 14, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Min Tae RYU, Sang Hoon UHM, Ki Seok LEE, Min Su LEE, Won Sok LEE, Min Hee CHO
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Patent number: 10770463Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: GrantFiled: June 11, 2019Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Publication number: 20200203351Abstract: A memory device includes: a substrate including a first active region and a second active region spaced apart from each other; a device isolation film on the substrate, the device isolation film defining the first active region and the second active region; and a buried word line structure passing a low dielectric region between the first active region and the second active region, wherein the buried word line structure includes a gate electrode in a gate trench and a gate insulating layer between a portion of the gate electrode outside the low dielectric region and the gate trench, and wherein an air gap is disposed between a portion of the gate electrode within the low dielectric region and the gate trench.Type: ApplicationFiled: September 7, 2019Publication date: June 25, 2020Inventors: Kyo-suk CHAE, Tai-uk RIM, Hyeon-kyun NOH, Won-sok LEE
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Publication number: 20190296017Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: MIN HEE CHO, JUN SOO KIM, HUI JUNG KIM, TAE YOON AN, SATORU YAMADA, WON SOK LEE, NAM HO JEON, MOON YOUNG JEONG, KI JAE HUR, JAE HO HONG
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Patent number: 10361205Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: GrantFiled: November 22, 2017Date of Patent: July 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Publication number: 20180301456Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: November 22, 2017Publication date: October 18, 2018Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Patent number: 8293604Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: GrantFiled: July 19, 2010Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Publication number: 20100285645Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: ApplicationFiled: July 19, 2010Publication date: November 11, 2010Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Patent number: 7781287Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: GrantFiled: January 30, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Publication number: 20080124869Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: ApplicationFiled: January 30, 2008Publication date: May 29, 2008Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Patent number: 7348628Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: GrantFiled: June 7, 2006Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Publication number: 20070012996Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: ApplicationFiled: June 7, 2006Publication date: January 18, 2007Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park