Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.

Abstract: A method and apparatus for thread synchronization is provided. The apparatus for thread synchronization includes a reader configured to generate a data read request, a writer configured to generate a data write request, a register file configured to have a full status indicating that the register file stores data and an empty status indicating that the register file stores no data, and a controller configured to receive the data read request from the reader or the data write request from the writer, and to process the received data read request or the received data write request while stalling or releasing the reader or the writer according to whether the register file is in the full status or in the empty status and according to an operating status of the reader or the writer.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract: A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract: A technology for reducing pipeline a control hazard is provided. A conditional branch is processed through a conditional branch prediction, and a predetermined conditional branch prediction, which is determined as incorrect, may be modified through a following test for the conditional branch prediction, thereby reducing the pipeline control hazard quickly without additional hardware.

Abstract: A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.

Abstract: A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Abstract: A processor for supporting a MIMO operation and method of processing a MIMO instruction are provided. The MIMO operation supporting processor may include a scheduler and at least one functional unit. The scheduler may map multiple inputs of the MIMO instruction to a plurality of sequential input cycles, respectively, and may map multiple outputs of the MIMO instruction to a plurality of sequential output cycles, respectively. The output cycles may be followed by the input cycles and a predetermined number of cycles for a MIMO operation. A functional unit may read a register during sequential input cycles, may perform a MIMO operation during a predetermined number of execution cycles, and may write the result of the MIMO operation into a register during sequential output cycles.

Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

Abstract: Capabilities are added to a Hardware Verification Language that facilitates the generation of test data. Random number sources, called random variables, can be produced by adding a randomness attribute to a variable declaration of a class definition. A “randomize” method call to a class instance produces a random value for each random variable. Constraint blocks, of a class definition, control random variables with constraint expressions. Dependency, of random variable value assignment, as determined by constraint expressions, can be expressed by a DAG. A constraint expression is converted into ranges of permissible values, from which a value is randomly chosen by a randomize method. A “boundary” method call sequentially selects a combination of boundary values, for each random variable, from each random variable's set of ranges. Coordinated selection of a boundary values permits all combinations of boundary values to be produced through successive boundary calls.

Abstract: A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources.

Abstract: An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When scheduling a plurality of recurrence loops, the apparatus first schedules a dominant loop whose loop head has no dependency on another loop among the recurrence loops.

Abstract: A semiconductor substrate is mounted on a semiconductor alignment apparatus. A chip alignment step is performed to center a central chip on the semiconductor substrate with respect to the semiconductor alignment apparatus, and to store the coordinates thereof. A semiconductor substrate alignment is performed to virtually align the semiconductor substrate with the semiconductor alignment apparatus. At this time, coordinates of a chip adjacent to the central chip and of a number of chips in a peripheral region of the semiconductor substrate are stored in the alignment apparatus. In addition, at least two templates are located in the central chip, and images and coordinates of the templates are stored in the semiconductor alignment apparatus during the semiconductor substrate alignment.

Abstract: A semiconductor substrate is mounted on a semiconductor alignment apparatus. A chip alignment step is performed to center a central chip on the semiconductor substrate with respect to the semiconductor alignment apparatus, and to store the coordinates thereof. A semiconductor substrate alignment is performed to virtually align the semiconductor substrate with the semiconductor alignment apparatus. At this time, coordinates of a chip adjacent to the central chip and of a number of chips in a peripheral region of the semiconductor substrate are stored in the alignment apparatus. In addition, at least two templates are located in the central chip, and images and coordinates of the templates are stored in the semiconductor alignment apparatus during the semiconductor substrate alignment.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions. The constraint expressions may impose a linear ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. A constraint_expression can constrain any random variable which has been declared at its level in the class hierarchy, or at any higher level.

Abstract: Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an “expect,” for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. Because random variables may also appear on the right-hand-side (rhs) of a constraint expression there is an ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs).