Patents by Inventor Won-Suck Yang

Won-Suck Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell structure for semiconductor memory device
    Patent number: 6246087
    Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: June 12, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chang-Jae Lee, Won-Suck Yang
  • Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
    Patent number: 6156601
    Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: December 5, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chang Jae Lee, Won Suck Yang, Kong Hee Park
  • DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
    Patent number: 5959321
    Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: September 28, 1999
    Assignee: LG Semicon, Ltd.
    Inventors: Chang Jae Lee, Won Suck Yang, Kong Hee Park
  • Memory cell structure for semiconductor memory device and fabricating method thereof
    Patent number: 5897350
    Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: April 27, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventors: Chang-Jae Lee, Won-Suck Yang