Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A flexible display device including a substrate, a light emitting layer, a first insulating layer, and a conductive layer. The substrate includes a bent region and a non-bent region. The light emitting layer overlaps the non-bent region. The first insulating layer is disposed on the substrate. The conductive layer is disposed on the first insulating layer. A sidewall of the first insulating layer includes a first tapered surface. The first tapered surface includes at least three curved surface portions continuously arranged with one another.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.