Patents by Inventor Won-Suk Yang
Won-Suk Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8049618Abstract: An indoor location system having a sensor and a method for checking an indoor location using the indoor location system are disclosed. The method includes: calculating a current location coordinate by using nodes; calculating a first movement distance by comparing the current location coordinate and a stored previous location coordinate; calculating a second movement distance through a sensor; and storing the current location coordinate instead of the previous location coordinate when the distance between the first movement distance and the second movement distance is smaller than a predetermined threshold value. Accordingly, an accurate location of an object can be recognized indoors and an error can be prevented from being caused when the location of the object is recognized.Type: GrantFiled: November 10, 2008Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Kweon Park, Won Suk Yang, Yun Je Oh, Joon Oo Kim, Jeong Rok Park, Sang Mook Lee, Jin Serk Baik, Do Young Ha
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Patent number: 7888198Abstract: An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.Type: GrantFiled: May 18, 1999Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Suk Yang, Ki-Nam Kim, Chang-Hyun Cho
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Publication number: 20100191733Abstract: A music linked photocasting service system and method are provided. The music linked photocasting service method includes reproducing music at the request of a user, analyzing a mood of the reproduced music at prescribed times, until music reproduction is completed, searching photographs suitable for a analyzed mood of the music, and displaying the searched photographs.Type: ApplicationFiled: January 29, 2010Publication date: July 29, 2010Inventors: Sung-Jin PARK, Won-Sang KWON, Won-Suk YANG, Chan-Seok YANG
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Publication number: 20100185987Abstract: An image management method and system are disclosed which can increase user convenience by reducing a display time of thumbnails in a DLNA system. The DLNA system includes a digital media server for generating a thumbnail group image using thumbnails corresponding to at least one original image file and transmitting the thumbnail group image, and a digital media player for receiving the thumbnail group image from the digital media server and requesting the digital media server to transmit an original image file corresponding to a selected thumbnail among thumbnails included the thumbnail group image.Type: ApplicationFiled: January 21, 2010Publication date: July 22, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-Seok Yang, Ho-Chul Shin, Byung-Soo Lim, Won-Suk Yang
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Patent number: 7602043Abstract: A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.Type: GrantFiled: July 31, 2006Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Cheol Lee, Won-Suk Yang, Jin-Woo Lee, Tae-Young Chung
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Publication number: 20090121867Abstract: An indoor location system having a sensor and a method for checking an indoor location using the indoor location system are disclosed. The method includes: calculating a current location coordinate by using nodes; calculating a first movement distance by comparing the current location coordinate and a stored previous location coordinate; calculating a second movement distance through a sensor; and storing the current location coordinate instead of the previous location coordinate when the distance between the first movement distance and the second movement distance is smaller than a predetermined threshold value. Accordingly, an accurate location of an object can be recognized indoors and an error can be prevented from being caused when the location of the object is recognized.Type: ApplicationFiled: November 10, 2008Publication date: May 14, 2009Inventors: Sung Kweon PARK, Won Suk Yang, Yun Je Oh, Joon Oo Kim, Jeong Rok Park, Sang Mook Lee, Jin Serk Baik, Do Young Ha
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Patent number: 7510963Abstract: A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad.Type: GrantFiled: November 16, 2004Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Won-suk Yang, Ki-nam Kim, Hong-sik Jeong
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Patent number: 7462523Abstract: A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.Type: GrantFiled: March 14, 2005Date of Patent: December 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Suk Yang, Sang-Hoo Song, Ki-Nam Kim, Hong-Sik Jeong
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Patent number: 7300888Abstract: An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.Type: GrantFiled: December 7, 2001Date of Patent: November 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-sik Jeong, Soo-ho Shin, Won-suk Yang, Ki-nam Kim
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Patent number: 7250335Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.Type: GrantFiled: August 11, 2005Date of Patent: July 31, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Won-suk Yang, Ki-nam Kim
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Publication number: 20070096191Abstract: A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.Type: ApplicationFiled: July 31, 2006Publication date: May 3, 2007Inventors: Eun-Cheol LEE, Won-Suk YANG, Jin-Woo LEE, Tae-Young CHUNG
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Patent number: 7164204Abstract: An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.Type: GrantFiled: February 3, 2004Date of Patent: January 16, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Won-suk Yang, Ki-nam Kim
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Publication number: 20050272251Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.Type: ApplicationFiled: August 11, 2005Publication date: December 8, 2005Inventors: Won-suk Yang, Ki-nam Kim
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Patent number: 6953959Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.Type: GrantFiled: May 28, 2002Date of Patent: October 11, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-suk Yang, Ki-nam Kim
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Publication number: 20050167717Abstract: A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Suk Yang, Sang-Hoo Song, Ki-Nam Kim, Hong-Sik Jeong
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Publication number: 20050151173Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: ApplicationFiled: December 28, 2004Publication date: July 14, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Patent number: 6900546Abstract: A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.Type: GrantFiled: March 4, 2002Date of Patent: May 31, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Suk Yang, Sang-Hoo Song, Ki-Nam Kim, Hong-Sik Jeong
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Publication number: 20050070094Abstract: A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad.Type: ApplicationFiled: November 16, 2004Publication date: March 31, 2005Inventors: Won-suk Yang, Ki-nam Kim, Hong-sik Jeong
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Patent number: 6855590Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: GrantFiled: August 28, 2003Date of Patent: February 15, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Patent number: 6836019Abstract: A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad.Type: GrantFiled: October 31, 2001Date of Patent: December 28, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-suk Yang, Ki-nam Kim, Hong-sik Jeong