Abstract: A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.

Abstract: A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.

Abstract: A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.