Abstract: Disclosure is a method for forming an alignment pattern of a semiconductor device.

Abstract: The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.

Abstract: The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.

Abstract: A method for fabricating a metal contact structure of semiconductor devices comprising forming a first conducting layer; a first insulating layer disposed on said first conducting layer; a first contact hole to said first conducting layer; wherein said first contact hole is formed in said first insulating layer; dummy conducting patterns formed in said first contact hole, wherein said conducting dummy patterns are contacted with said first conducting layer through said first contact hole, and said dummy film is partly overlapped on the said first insulating layer; a second insulating layer disposed on said first insulating layer; a second contact hole, wherein said second contact hole is formed in said second insulating layer, and wherein said first contact hole and said second contact hole substantially form a through-hole; and a second conducting layer disposed on said second insulating layer which is contacted to said dummy conducting patterns through said second contact hole.