Abstract: A distortion compensation apparatus heightens resolution of a low frequency domain among the audible frequency band, and relatively lowers the resolution in the higher frequency domain. By performing the band division using a Bark scale, filter coefficients are determined. The acoustic signal of the entire audible frequency band which does not pass a low-pass filter is distortion-compensated by a first filter portion. The acoustic signal of the divided band, which is obtained by passing the low-pass filter, is filtered so as to remove a portion of the distortion which is not compensated by signal distortion compensation of the entire audible frequency band by means of a second filter portion. Then, the filtered signal is added to the distortion-compensated acoustic signal of the entire audible frequency band. The remaining signal distortion portion in the distortion compensated acoustic signal by the first filter portion is removed by the signal output from the second filter.

Abstract: A recorder for an IC memory card (37) using a NAND-type flash memory assigns a single address to both audio and video source data, matching a structure of the NAND-type flash memory. Consequently, the audio and video source data may be recorded with a single address. The recorder includes a first memory (32) for accessing video data in units of a basic region of one page in the NAND-type flash memory, and a second memory (33) for accessing audio data in units of a dummy region of one page in the NAND-type flash memory. A first latch (34) and a second latch (35) match the timing of the video data and the audio data, respectively, accessible from the memories (32, 33). A page memory (36) records the video data output via the first latch (34) and then records the audio data output via the second latch (35) sequentially to thereby store data of a whole one-page unit.

Abstract: A NAND-type flash memory integrated circuit card is composed of an input and output bus having first lines for a plurality of NAND-type flash memory components having first and second groups, first lines for zone address data, instruction data, address data and information data, and second lines for the information data only, a first buffer for transmitting the data between the first lines and the NAND-type flash memory components of the first group, a second buffer for transmitting the data between the first lines and the NAND-type flash memory components of the second group, a third buffer for transmitting the data between the second lines and the NAND-type flash memory components of the second group, and a controller for enabling one of the plurality of the NAND-type flash memory components according to the mode control signal, the zone address data and the address data, and one of the first through third latches, in order to instruct one mode among a word mode, a half-word mode for upper eight bits, a byt