Abstract: A method of operating a computing device according to an aspect of the inventive concept may include accessing a page of a second tier memory, checking a time taken for the access, checking a total number of accesses of the page based on the time taken for the access, and determining whether to terminate promotion of the page to the first tier memory and a timing of the promotion, based on the total number of accesses of the page.

Abstract: An accelerator includes a computation circuit configured to perform a neural network operation using a token included in input data and a first parameter set; a main memory; and a control circuit configured to request the first parameter set from an external device or the main memory, and to provide the first parameter set to the computation circuit, wherein the control circuit is configured to prefetch one or more parameter sets from a plurality of parameter sets based on neural network usage information including number of tokens processed by each of a plurality of neural networks.

Abstract: In a method for operating a quantum computing system and a quantum computing system, the method for operating a quantum computing system may include: generating, by the QPU, a probability distribution of a quantum state by executing a quantum circuit; outputting, by the QPU, a measurement result of the quantum state as classical data; determining, by the classical processor, an information entropy for the probability distribution of the quantum state based on the classical data; determining, by the classical processor, the number of measurement shots of the QPU according to the information entropy; delivering, by the classical processor, the determined number of measurement shots to the QPU; and iteratively measuring, by the QPU, the quantum circuit with the determined number of measurement shots.

Abstract: A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.

Abstract: A method of operating a computing device according to an aspect of the inventive concept may include accessing a page of a second tier memory, checking a time taken for the access, checking a total number of accesses of the page based on the time taken for the access, and determining whether to terminate promotion of the page to the first tier memory and a timing of the promotion, based on the total number of accesses of the page.

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

Abstract: An apparatus and method with register sharing are provided. In one general aspect, a method of operating a processing apparatus includes determining whether there is shared data that is used by each of threads in a plurality of threads sharing a shared memory, based on an instruction that has been decoded, based on determining whether there is shared data that is used by each of the threads in the plurality of threads, determining whether an address of the shared data corresponding to each of the threads in the plurality of threads is stored in an address-to-register mapping table, based on a result of either the determining whether the address is stored in the address-to-register mapping table, mapping the address of the shared data to a shared register corresponding to the shared data, and loading the shared data based on the shared register.

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

Abstract: Disclosed is a memory system using a heterogeneous data format, which provides a personalized recommendation algorithm function to an internet service user based on a plurality of items, which includes a user preference analyzer for each item that calculates a user preference value corresponding to each item of a analysis target service; and a memory that stores data related to the each item in a first data format or stores data related to the each item in a second data format with required bits less than the first data format, based on the user preference value of the each item.

Abstract: Disclosed is an accelerator and a method of operating the accelerator including determining whether any group shares weights of a first group from among groups, determining a presence of an idle processing element (PE) array, in response to no group sharing the weights of the first group, and selecting a second group having a memory time overlapping a computation time of the first group from among the groups, in response to the idle PE array being present.

Abstract: A network scheduling device and method are disclosed. The scheduling method comprises: determining whether a set condition for a transmission time interval (TTI) is satisfied, and, if the set condition is satisfied, storing in a memory, at each TTI until the set TTI elapses, a data array comprising the network state of the current TTI, the scheduler type selected at the network state of the current TTI, the network state of the next TTI, and the actual compensation value for the network state of the current TTI, and updating the parameters of the first neural network based on at least one of the data arrays stored in the memory, and, if the set condition is not satisfied, inputting the network state of the current TTI to the first neural network and selecting a scheduler using the output of the first neural network based on the input network state of the current TTI.

Abstract: A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.

Abstract: A method of operating a network switch for collective communication includes: receiving, via a network from external electronic devices, a first and second matrix each formatted according to a sparse matrix storage format; and generating a third matrix formatted according to the sparse matrix storage format, wherein the third matrix is generated by combining the first and second matrix according to the sparse matrix storage format, wherein, according to the sparse matrix storage format the first matrix includes first matrix positions of respective first element values and the second matrix includes second matrix positions of respective second element values, and wherein the combining includes comparing the first matrix positions with the second matrix positions.

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

Abstract: An apparatus and method with register sharing are provided. In one general aspect, a method of operating a processing apparatus includes determining whether there is shared data that is used by each of threads in a plurality of threads sharing a shared memory, based on an instruction that has been decoded, based on determining whether there is shared data that is used by each of the threads in the plurality of threads, determining whether an address of the shared data corresponding to each of the threads in the plurality of threads is stored in an address-to-register mapping table, based on a result of either the determining whether the address is stored in the address-to-register mapping table, mapping the address of the shared data to a shared register corresponding to the shared data, and loading the shared data based on the shared register.

Abstract: A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.

Abstract: A processing device including a first buffer storing calculation rules, a calculator including a plurality of multipliers and an adder, the multipliers configured to perform multiplication repeatedly, a second buffer storing operands, the second buffer being configured to enqueue the operands based on the calculation rules into a queue, and a counter indicating a respective number indicating a number of times a multiplication is to be performed by each of the plurality of multipliers, each multiplier of the plurality of multipliers being configured to provide a non-final multiplication result to a first path to an input of the corresponding multiplier responsive to a corresponding number of multiplications performed by the multiplier being less than the respective number, and provide a final multiplication result to a second path to the adder responsive to the corresponding number of multiplications performed by the multiplier being equal to the respective number.