Abstract: Provided are a method and apparatus for providing a network switching service to a user equipment.

Abstract: Provided are a method and apparatus for a user equipment, a core network, and a second device to enable bidirectional communication for second devices. The method of the second device may include receiving internet protocol (IP) configuration information for automatically configuring an IP version 6 (IPv6) address of the second device from a core network through a user equipment; generating the IPv6 address using information in the IP configuration information; and transmitting the generated IPv6 address to the core network through the UE.

Abstract: Provided are a method and apparatus for providing a multi virtual local area network service to user equipments.

Abstract: Provided is a positive electrode active material which includes an inner region that is a region from the center of the positive electrode active material particle to R/2; and an outer region that is a region from R/2 to the surface of the positive electrode active material particle, wherein R is a distance from the center of the positive electrode active material particle to the surface thereof. The positive electrode active material further includes 30% to 80% of crystallites A with respect to a total number of crystallites in the outer region of the positive electrode active material, the crystallites A having high crystallite long-axis orientation degree and crystallite c-axis orientation degree. Thus, the positive electrode active material can achieve excellent capacity characteristics and service life characteristics.

Abstract: An apparatus for measuring a concentration of a target gas includes: a gas sensor including a sensing layer having an electric resistance that changes by an oxidation reaction or a reduction reaction between gas molecules and the sensing layer; and a processor configured to, in response to the target gas being introduced along with air into the gas sensor, monitor a change of the electric resistance of the sensing layer and determine the concentration of the target gas by analyzing a shape of the change of the electric resistance.

Abstract: A balancer includes a balancer housing coupled to a drum of a washing machine, the balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, at least one magnet to restrain movement of the mass along the channel when rotational speed of the drum is within a predetermined range, and at least one magnet fixing member coupled to an outside of the balancer housing to receive and fix the magnet.

Abstract: A balancer includes a balancer housing coupled to a drum of a washing machine, the balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, at least one magnet to restrain movement of the mass along the channel when rotational speed of the drum is within a predetermined range, and at least one magnet fixing rib formed at one side of the balancer housing to fix the magnet.

Abstract: A washing machine having a balancer to offset unbalanced load generated during rotation of a drum. The washing machine includes a cabinet, a drum rotatably disposed in the cabinet, and a balancer mounted to the drum to offset unbalanced load generated in the drum during rotation of the drum. The balancer includes a balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, a magnet provided at one side of the balancer housing to restrain the mass, and a magnet case to receive the magnet.

Abstract: A balancer includes a balancer housing coupled to a drum of a washing machine, the balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, at least one magnet to restrain movement of the mass along the channel when rotational speed of the drum is within a predetermined range, and at least one magnet fixing rib formed at one side of the balancer housing to fix the magnet.

Abstract: A balancer includes a balancer housing coupled to a drum of a washing machine, the balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, at least one magnet to restrain movement of the mass along the channel when rotational speed of the drum is within a predetermined range, and at least one magnet fixing member coupled to an outside of the balancer housing to receive and fix the magnet.

Abstract: A washing machine having a balancer to offset unbalanced load generated during rotation of a drum. The washing machine includes a cabinet, a drum rotatably disposed in the cabinet, and a balancer mounted to the drum to offset unbalanced load generated in the drum during rotation of the drum. The balancer includes a balancer housing having an annular channel defined therein, at least one mass movably disposed in the channel, a magnet provided at one side of the balancer housing to restrain the mass, and a magnet case to receive the magnet.

Abstract: An apparatus and method for measuring the characteristics of a semiconductor device is disclosed. The measuring apparatus may include first to M-th (wherein M is a positive integer not less than 1) starved devices each being biased in response to a bias voltage varying in accordance with a variable first supply voltage, thereby varying an amount of current flowing through a semiconductor device included in the starved device. Interconnect lines may interconnect the first to M-th starved devices. A measuring unit measures at least one of a delay time caused by the semiconductor devices of the starved devices themselves, and a compound delay time caused by the semiconductor devices of the starved devices themselves plus a delay time caused by the interconnect lines. The measured results can be analyzed under conditions more approximate to diverse situations exhibited in practical chips in accordance with development of manufacturing processes and techniques.

Abstract: A washing machine includes a tub to contain water and a drum rotatably installed within the tub. The drum includes a cylindrical body and a front member made of resin, provided with a disc-shaped race formed therein and covering the front surface of the body. The race of the front member and a mass body in the race function as a balancer.

Abstract: An apparatus and method for measuring the characteristics of a semiconductor device is disclosed. The measuring apparatus may include first to M-th (wherein M is a positive integer not less than 1) starved devices each being biased in response to a bias voltage varying in accordance with a variable first supply voltage, thereby varying an amount of current flowing through a semiconductor device included in the starved device. Interconnect lines may interconnect the first to M-th starved devices. A measuring unit measures at least one of a delay time caused by the semiconductor devices of the starved devices themselves, and a compound delay time caused by the semiconductor devices of the starved devices themselves plus a delay time caused by the interconnect lines. The measured results can be analyzed under conditions more approximate to diverse situations exhibited in practical chips in accordance with development of manufacturing processes and techniques.

Abstract: Embodiments relate to a semiconductor technology, and more particularly, to a modeling structure for simulation of a trapezoidal metal line. The modeling structure for simulation of a trapezoidal metal line includes a top step with a width A, a bottom step with a width B, a middle step with a width equal to an average of the width A and the width B, and a total height C, wherein the middle step has a height equal to a value obtainable by subtracting both a height of the top step and a height of the bottom step from the total height C.

Abstract: The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

Abstract: The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

Abstract: A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.

Abstract: This invention relates to a semiconductor device and method for fabricating the semiconductor device, for forming a source and drain structure having no side diffusion. The semiconductor device includes a silicon substrate, a gate formed on the silicon substrate with a gate insulation film in between, and a source and drain formed of conductive material layers buried in the substrate to a designated depth at opposite sides of the gate, thereby providing a source with no side diffusion, preventing reduction of channel length, and improving element integration.

Abstract: This invention relates to a nonvolatile semiconductor memory element having elevated source and drain regions, a well-shaped floating gate surrounding a control gate, and leveled surface, and a method for fabricating the same.