Abstract: A semiconductor package includes a first chip including a first substrate, a first wiring layer on the first substrate, and a plurality of through-electrodes to be connected to the first wiring layer and protruding from a lower surface of the first substrate, a double gap-fill layer covering a side surface and a lower surface of the first chip and a protruding portion of the through-electrode and having a double layer structure, a second chip disposed on the first chip and the double gap-fill layer, including a second wiring layer and a second substrate on the second wiring layer, and bonded to the first chip by hybrid bonding, and a bump on a lower surface of the first chip and connected to the through-electrode.

Abstract: A semiconductor package includes a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of cavities, and a plurality of wiring layers respectively disposed on the plurality of insulating layers, a semiconductor chip disposed on an upper surface of the coreless circuit substrate and electrically connected to an uppermost wiring layer among the plurality of wiring layers, and a plurality of semiconductor-based chip capacitors disposed in the plurality of cavities, respectively, and each having an upper surface on which first pads are disposed and a lower surface on which second pads are disposed. The first pads are connected to a first wiring layer, adjacent to the first pads, among the plurality of wiring layers by conductive bumps, and the second pads are connected to an interconnection via of a second wiring layer, adjacent to the second pads, among the plurality of wiring layers.

Abstract: Provided is a wiring structure including a wiring insulating layer including a first insulating layer and a second insulating layer on the first insulating layer, and a wiring pattern that penetrates the second insulating layer and extends into the first insulating layer, wherein a portion of a side surface of the wiring pattern in contact with the first insulating layer is a curved surface with a first surface roughness, and a portion of the side surface of the wiring pattern in contact with the second insulating layer is a flat surface with a second surface roughness that is less than the first surface roughness.

Abstract: A method of manufacturing a semiconductor package with a semiconductor chip including an active surface and an inactive surface opposite to the active surface is presented. The method includes attaching, to the active surface, a film structure including an insulating layer and a first seed layer contacting the insulating layer. A via hole is formed by penetrating the insulating layer and the first seed layer followed by a descumming the insulating layer and the first seed layer in which the via hole is formed. A second seed layer is formed on the insulating layer and on the first seed layer on which the descum process was performed. A photoresist pattern on the second seed layer enables forming a conductive via by filling both a space defined by the via hole with a conductive material and by filling a space defined by the photoresist pattern with the conductive material.

Abstract: A semiconductor package includes a first chip including a first substrate, a first wiring layer on the first substrate, and a plurality of through-electrodes to be connected to the first wiring layer and protruding from a lower surface of the first substrate, a double gap-fill layer covering a side surface and a lower surface of the first chip and a protruding portion of the through-electrode and having a double layer structure, a second chip disposed on the first chip and the double gap-fill layer, including a second wiring layer and a second substrate on the second wiring layer, and bonded to the first chip by hybrid bonding, and a bump on a lower surface of the first chip and connected to the through-electrode.

Abstract: A semiconductor package includes a redistribution substrate having a first surface and a second surface opposite to each other, and including a plurality of first photosensitive insulating layers and a plurality of redistribution layers disposed among the plurality of first photosensitive insulating layers; at least one semiconductor chip disposed on the first surface of the redistribution substrate and including a plurality of contact pads electrically connected to the plurality of redistribution layers; a protective insulating layer including a second photosensitive insulating layer disposed on the second surface of the redistribution substrate and having a plurality of contact holes, and a non-photosensitive insulating layer disposed on an outer surface of the second photosensitive insulating layer and an internal sidewall of each of the plurality of contact holes; and a plurality of under bump metallurgy (UBM) connectors each having a UBM pad disposed on the protective insulating layer and a UBM via dispo

Abstract: A semiconductor package may include: a first redistribution substrate; a semiconductor chip disposed on the first redistribution substrate; a second redistribution substrate; an encapsulant disposed between the first redistribution substrate and the second redistribution substrate and encapsulating the semiconductor chip; and a connection structure disposed in the encapsulant, connecting an upper surface of the first redistribution layer substrate and a lower surface of the second redistribution substrate, and to include a paste bump.