Abstract: An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer.

Abstract: An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

Abstract: A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.

Abstract: A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a reaction chamber is provided, wherein said wafer comprises a first conductive layer. Then, a first dielectric layer is formed above said first conductive layer to prevent said first conductive layer from growing silicon oxide and to diminish leakage current. Next a precursor is transmitted to a vaporizer. Then said precursor is transformed to a gas and said gas is transmitted to said reaction chamber. Next, a second dielectric layer is deposited above said first dielectric layer. Then a heat treatment is proceeded and a second conductive layer is formed on said second dielectric layer.

Abstract: Methods are presented for reducing the thermal budget in a semiconductor manufacturing process that include for instance, depositing high dielectric constant films to form MIS capacitors, where processes including plasma nitridation and oxidation and deposition processes including ALD and PVD are selectively employed to lower the overall thermal budget thereby allowing smaller structures to be reliably manufactured.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

Abstract: Within a method for fabricating a capacitor structure and a capacitor structure fabricated employing the method, there is provided a conductor barrier layer formed upon an upper capacitor plate formed within the capacitor structure. There is also provided a silicon layer formed upon the conductor barrier layer. The conductor barrier layer and the silicon layer provide for enhanced interdiffusion stability and enhanced delamination stability with respect to the upper capacitor plate, and thus enhanced reliability and performance of the capacitor structure.

Abstract: A method of fabricating a strained-silicon structure comprising the following steps. A substrate having an insulator layer formed thereover is provided. A silicon-on-insulator layer is formed over the insulator layer. A first SiGe layer is formed over the silicon-on-insulator layer. The first SiGe layer being strained. At least the first SiGe layer is annealed to convert the strained SiGe layer to a relaxed first SiGe layer. A second SiGe layer, having the same composition as the first SiGe layer, is formed over the first SiGe layer. The second SiGe layer being relaxed. An epitaxial silicon layer is grown over the second SiGe layer. The epitaxial silicon layer being strained to complete formation of the strained-silicon structure.

Abstract: Within a method for fabricating a capacitor structure and a capacitor structure fabricated employing the method, there is provided a conductor barrier layer formed upon an upper capacitor plate formed within the capacitor structure. There is also provided a silicon layer formed upon the conductor barrier layer. The conductor barrier layer and the silicon layer provide for enhanced interdiffusion stability and enhanced delamination stability with respect to the upper capacitor plate, and thus enhanced reliability and performance of the capacitor structure.

Abstract: Methods are presented for reducing the thermal budget in a semiconductor manufacturing process that include for instance, depositing high dielectric constant films to form MIS capacitors, where processes including plasma nitridation and oxidation and deposition processes including ALD and PVD are selectively employed to lower the overall thermal budget thereby allowing smaller structures to be reliably manufactured.

Abstract: Within both a method for forming a capacitor and a capacitor formed employing the method, there is employed for forming at least part of at least one of a first capacitor plate and a second capacitor plate a tungsten rich tungsten oxide material having a tungsten:oxygen atomic ratio of from about 5:1 to about 1:1. By forming the at least part of the at least one of the first capacitor plate and the second capacitor plate of the foregoing tungsten rich tungsten oxide material, the capacitor is formed with attenuated leakage current density.

Abstract: A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening.

Abstract: A method for improving the interface between a silicon nitride film and a silicon surface is described. According to the present invention a silicon nitride film is formed on a silicon surface of a substrate. While said substrate is heated the silicon nitride film is exposed to an ambient comprising hydrogen (H2). In a prefered embodiment of the present invention the ambient comprises H2 and N2.

Abstract: A method for forming a dielectric-constant-enhanced capacitor includes depositing a silicon nitride layer on polysilicon layer first, then a dielectric-constant-enhanced Tantalum-oxide-based film is deposited next, and a metal layer is deposited last. The dielectric-constant-enhanced film is produced by chemical vapor deposition and composed of a mixture of tantalum oxide and titanium oxide wherein the ratio of Ti to Ta is in range from 5 to 15 mole percent. The dielectric constant is greatly improved by a factor of 2 to 3.5 in this invention. After the dielectric-constant-enhanced thin film has been deposited, the heat treatment procedure will be proceed to diminish the leakage current greatly, when it is used in a capacitor.

Abstract: A method of fabricating a dielectric layer which is application to be used in a capacitor. A first conductive layer is provided. A nitridation step is performed on the first conductive layer, so that a nitride layer is formed on a surface of the first conductive layer. A dielectric layer with a high dielectric constant is formed, followed by a thermal treatment and an oxygen plasma treatment to terminate dangling bonds of the dielectric layer. Consequently, oxygen is distributed on a surface of the dielectric layer and bonded with dangling bonds of the dielectric layer distributed on the surface.

Abstract: A method for improving the interface between a silicon nitride film and a silicon surface is described. According to the present invention a silicon nitride film is formed on a silicon surface of a substrate. While said substrate is heated the silicon nitride film is exposed to an ambient comprising hydrogen (H.sub.2). In a prefered embodiment of the present invention the ambient comprises H.sub.2 and N.sub.2.