Abstract: A method of displaying a memo is provided. The method includes displaying an electronic document and a memo for the electronic document, obtaining relative position information of the memo on the electronic document, and displaying the memo on the electronic document based on the obtained position information depending on a display state of the electronic document.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: A signal gating controller for recovering true data signal pulses while gating out false data signal pulses which are generated and prevent convergence when recovering a multilevel data signal, such as an MLT3 Ethernet signal, which has been severely over-equalized. A signal slicing circuit generates two data peak signals: one data peak signal identifies occurrences of positive data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and positive peak signal levels; the other data peak signal identifies occurrences of negative data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and negative peak signal levels. A signal gating control circuit sequentially latches such data peak signals to produce two gating control signals.

Abstract: A gain controller for a signal mixer in which consistent circuit gain is maintained by using transistors in the gain control and signal mixing stages with equal corresponding device dimensions and by using a differential gain control voltage with inverse and noninverse differential voltage phases which individually track variations in the dc bias currents used to power the gain control and signal mixing stages. This provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures by tracking variations in the dc biasing used to power the gain control and signal mixing stages.

Abstract: A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.

Abstract: A closed feedback loop controls the baseline correction of a data signal. Detected signal information about the baseline and positive and negative peaks of the incoming data signal is processed to generate a baseline correction signal which identifies the difference, if any, between the present data signal baseline and that which is desired. This baseline correction signal is summed with the original data signal to bring its baseline into conformance with the desired baseline.

Abstract: A closed feedback loop controls the adaptive equalization of an incoming data signal received via a cable. Detected signal information about the positive and negative peaks of the incoming data signal during different windows in time is processed to generate a set of adaptive equalization control signals which identify differences, if any, between the positive and negative peaks of the present data signal and those which are desired. These equalization control signals control an input signal equalization circuit which adaptively adjusts the waveshape of the present data signal to bring it into conformance with the desired waveshape.

Abstract: A mixing circuit for combining biasing and signals using a selectively variable signal gain which is independent of the biasing and using biasing which is independent of the selectively variable signal gain. A Gilbert cell is used to multiply a differential control voltage, which represents a normalized signal gain factor, with input currents which include biasing components and input signal components. The resultant output current includes a bias component which is independent of the differential control voltage and a signal component which is independent of the input current biasing components. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage.

Abstract: A distributive encoder for receiving and processing digital error signals representing variations in peak values of an equalized incoming digital data signal and in accordance therewith encoding error signals which represent signal peak errors in data signals for purposes of identifying erroneous signal baseline, peak and equalization conditions. The digital error signals represent variations in peak values of an equalized incoming digital data signal which includes a data signal baseline intermediate to its positive and negative peaks. Two sets of the digital error signals identify when present positive and negative levels transcend prior positive and negative levels, respectively, of the equalized incoming digital data signal. Using various subsets of these digital error signals, the distributive encoder generates encoded error signals which identify erroneous signal baseline, peak and equalization conditions.

Abstract: A method and circuitry are provided for generating a phase shift in the recovered clock in a high speed, digital data recovery phase locked loop. Since phase step injection can be done in a closed loop environment, the dynamic of the real time phase step response of the PLL can be analyzed using a phase meter. In an open-loop environment, the output of the phase meter with a step response of 60 degree phase shift tracks closely with the internal RC response at the multi-phase outputs of the PLL's phase-to-frequency converter. Since the register and capacitor values vary with process, the scheme for verifying the relative accuracy of the PLL's internal filters can be verified without actually probing the device.

Abstract: A phase-to-frequency converter uses a triangular waveform synthesizer to generate a triangular wave using both PDM and a DC modulation scheme. A 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the multiple phases of the triangular waveform. The generated multiple phases of the triangular wave are then modified by reducing the ramp rate at appropriate points to suppress the third harmonic and its multiples. The ramp rate is proportional to the pulse density output of the Pulse Density Modulator. In one embodiment, the rate of the PDM output is reduced by one half during appropriate periods by gating the output by its clock, thereby reducing its density by one half during those periods.

Abstract: A triangular waveform synthesizer for a phase-to-frequency converter generates a saw tooth and triangular wave using both PDM and a DC modulation scheme. To minimize both delay and logic, while continuing to provide reasonable resolution, a 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. Since the switching and adding of the DC levels occurs in real time, the actual delay for the resultant triangular wave is only that of the 4-bit PDM.

Abstract: A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal.

Abstract: This disclosure describes a recorder/playback system which utilizes a silicon chip having bipolar transistors. One feature is an integral electronic switching arrangement which permits silent and smooth change from the record to the playback mode and vice versa by operation of an external single pole switch. Other features include a circuit for driving a recording level meter, an automatic audio level control circuit (ALC) and integral voltage and current regulators.