Patents by Inventor Wong Kwet Nam

Wong Kwet Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680686
    Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 25, 2014
    Assignee: Spansion LLC
    Inventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Thor Lee Lee, Sally Foong, Kevin Guan
  • Patent number: 8357563
    Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 22, 2013
    Assignee: Spansion LLC
    Inventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Koo Eng Luon, Sally Foong, Kevin Guan
  • Publication number: 20120038059
    Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Koo Eng LUON, Sally FOONG, Kevin GUAN
  • Publication number: 20110316158
    Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Thor Lee LEE, Sally FOONG, Kevin GUAN
  • Patent number: 7799612
    Abstract: Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: September 21, 2010
    Assignee: Spansion LLC
    Inventors: Sally Foong, Tan Kiah Ling, Kee Cheng Sim, Wong Kwet Nam, Yue Ho Foong
  • Patent number: 7157376
    Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sally Y. L. Foong, Lim See-Kee, Wong Kwet Nam