Abstract: A lower module of a power electronic device includes a lower module included in a power electronic device that is divided into an upper module and a lower module by an intermediate plate and comprises a blower fan to introduce air into the inner space of the lower module; a plurality of capacitors installed in a suspended form on the intermediate plate and spaced apart from the blower fan; a heat sink having a plurality of heat dissipation fins through which heat generated from a heating component disposed on the upper module is conducted, and disposed adjacent to the capacitors to cool the plurality of heat dissipation fins by air moved from the plurality of capacitors; a DC reactor cooled by the air moved from the heat dissipation fins; and a discharge plate having a vent hole to discharge the air moved from the DC reactor to the outside.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.

Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: The present invention relates to: a fusion polypeptide in which an anti-inflammatory polypeptide and a ferritin monomer fragment are bound; and a pharmaceutical composition for treating inflammatory diseases, containing the same as an active ingredient and, more specifically, to: a fusion polypeptide in which an anti-inflammatory polypeptide is fused to an N-terminus and/or a C-terminus of a ferritin monomer fragment from which a portion of a fourth loop and a fifth helix, of a human derived ferritin monomer, are removed; and a use thereof for treating inflammatory diseases.

Abstract: The present invention relates to: a fusion polypeptide in which an anti-inflammatory polypeptide and a ferritin monomer fragment are bound; and a pharmaceutical composition for treating inflammatory diseases, containing the same as an active ingredient and, more specifically, to: a fusion polypeptide in which an anti-inflammatory polypeptide is fused to an N-terminus and/or a C-terminus of a ferritin monomer fragment from which a portion of a fourth loop and a fifth helix, of a human derived ferritin monomer, are removed; and a use thereof for treating inflammatory diseases.

Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.

Abstract: A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a connector. The heat-transferring part may be configured to have a thermal conductivity higher than the substrate. Accordingly, during the operation of the semiconductor module, the connector can have a temperature lower than the devices.

Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.

Abstract: A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a connector. The heat-transferring part may be configured to have a thermal conductivity higher than the substrate. Accordingly, during the operation of the semiconductor module, the connector can have a temperature lower than the devices.

Abstract: In one embodiment, the method includes disposing a first chip over a package substrate. The first chip has at least one first chip pad. The method further includes forming a first bonding wire connected to the first chip pad and the package substrate, and disposing a second chip over at least a portion of the first chip. The second chip has at least one second chip bonding pad. A first bonding wire is formed electrically connected to the second chip bonding pad and the first bonding wire.

Abstract: In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.

Abstract: In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.

Abstract: In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.

Abstract: In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.