Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

Abstract: Manufacturing integrated circuit (IC) devices having adjacent transistors with different channel materials. A transistor includes a stack of nanoribbons coupling source and drain bodies, and a nanoribbon has a thickness at a midpoint of the nanoribbon greater than a thickness away from the midpoint. A second transistor may include a stack of nanoribbons coupling source and drain bodies, and the first transistor nanoribbons may have larger thickness variations than the second transistor nanoribbons. The first transistor nanoribbons may have a first element also in the second transistor nanoribbons and a second element absent in the second transistor nanoribbons. The second element may be added into the first transistor nanoribbons by depositing on the first transistor nanoribbons a layer having the second element, depositing a retaining layer over the second-element layer, and diffusing the second element into the first transistor nanoribbons.

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.