Abstract: A semiconductor package includes a substrate including bonding pads, first semiconductor chips stacked on the substrate, first connection members disposed on the substrate and the first semiconductor chips, each first connection member electrically connecting a corresponding first bonding pad to each first semiconductor chip, and connection bumps disposed below the substrate and electrically connected to the bonding pads. Each first semiconductor chip includes first connection pads adjacent to a first edge of the first front surface, a passivation layer disposed on the first front surface, and first trenches disposed in the passivation layer and extending from the first edge of the first front surface toward the first connection pads. Each first trench exposes at least a portion of a corresponding first connection pad.

Abstract: A semiconductor package and a method of manufacturing the same are provided such that the total thickness of a package and the pitch of a chip pad are decreased thereby reducing cracks in wiring. The semiconductor package includes a package substrate, at least two semiconductor chips stacked on the package substrate, in a stepped structure, a side insulation layer disposed on one side surface of each of the at least two semiconductor chips, and a conductive connection pattern disposed on a slope surface of the side insulation layer, a portion of an upper surface of each of the at least two semiconductor chips, and a portion of an upper surface of the package substrate, the conductive connection pattern connecting the at least two semiconductor chips to the package substrate, wherein the conductive connection pattern includes a straight line portion and a bent line portion.

Abstract: A semiconductor package includes a first semiconductor chip, a lower redistribution structure electrically connected to the first semiconductor chip, an upper redistribution structure on the first semiconductor chip, a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure, and a first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure to dissipate heat of the first semiconductor chip.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip stack, an interposer and a molding member. The semiconductor chip stack may include a first semiconductor chip on the package substrate and second semiconductor chips stacked on the first semiconductor chip in a vertical direction. End portions in a first horizontal direction of the second semiconductor chips may not be aligned with each other in the vertical direction. The interposer may be disposed between the package substrate and the semiconductor chip stack, and may at least partially overlap the semiconductor chip stack in the first horizontal direction and include a wiring structure. The molding member may be disposed on the package substrate, and may cover the semiconductor chip stack and the interposer. The package substrate may include a hole extending in the vertical direction through a portion of the package substrate between the first semiconductor chip and the interposer.

Abstract: A semiconductor package may include a package substrate including first and second surfaces, which are opposite to each other, a first semiconductor chip on the first surface, a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on the second surface, a second mold layer on the second surface of the package substrate, bottom and side surfaces of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip, a vertical conductive pillar provided to penetrate the second mold layer in a vertical direction and horizontally spaced apart from the second and third semiconductor chips, and connection terminals between a bottom surface of the first semiconductor chip and the first surface. The vertical conductive pillar may be placed on the second surface.

Abstract: A semiconductor package may include a substrate including an upper surface including a first upper pad; first semiconductor chips stacked on the substrate; and a first controller structure in contact with a side surface of at least one of the first semiconductor chips. The first controller structure may include a first controller chip, a first insulating film, and a first conductive film. A first surface of the first controller chip may face a first horizontal direction and may include a first contact pad disposed thereon. The first insulating film may expose the first contact pad and may extend along the first surface of the first controller chip to the substrate. The first conductive film may cover the first contact pad of the first controller chip and the first upper pad of the substrate.

Abstract: A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

Abstract: A semiconductor package includes a substrate including bonding pads, semiconductor chips stacked on the substrate and each including a lower surface and an upper surface, and connection pads on the upper surface, connection films spaced apart from each other in a first direction, the connection films electrically connecting the connection pads and corresponding ones of the bonding pads to each other in a second direction intersecting the first direction, a mold covering the semiconductor chips and the connection films, and connection bumps being under the substrate, the connection bumps electrically connected to the bonding pads. Each of the connection films includes a flexible film covering at least two connection pads adjacent to each other in the first direction, among the connection pads, and conductive lines extending in the second direction on the flexible film, the conductive lines respectively connected to the at least two connection pads.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.

Abstract: A semiconductor package includes a package substrate including an insulating layer, an interconnection circuit, and upper pads and lower pads electrically connected through the interconnection circuit, a plurality of semiconductor chips stacked including connection pads, a support structure contacting a side surface of a first semiconductor chip, which is an uppermost one among the plurality of semiconductor chips and at least a portion of an upper surface of a second semiconductor chip, which is one among the plurality of semiconductor chips below the first semiconductor chip, a first connection structure connecting the upper pads of the package substrate to the connection pads of the second semiconductor chip, a second connection structure connecting the connection pads of the first semiconductor chip to the connection pads of the second semiconductor chip, and an encapsulant covering the plurality of semiconductor chips, the first connection structure, and the second connection structure.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.

Abstract: A semiconductor package includes a package substrate including substrate pads on an upper portion of the package substrate, a first semiconductor chip on the package substrate, a first chip pad on the first semiconductor chip, a first conductive connection pattern on an upper surface of the first chip pad, an upper surface of the first semiconductor chip, and an upper surface of a first substrate pad among the substrate pads, and a first insulation layer on the package substrate and covering the first semiconductor chip, the first chip pad and the first conductive connection pattern.

Abstract: A semiconductor package includes a package substrate including upper pads, semiconductor chips stacked in a first direction and each semiconductor chip including bonding pad structures respectively disposed at one side of an upper surface thereof and spaced apart from each other in a second direction, first connection bumps on the bonding pad structures, each first connection bump electrically connected to a respective bonding pad structure, second connection bumps on the upper pads, each second connection bump electrically connected to a corresponding bonding pad structure and a corresponding upper pad, an interconnection pattern extending in a third direction on the package substrate and the semiconductor chips and electrically connecting each of the first connection bumps at each level to a corresponding first connection bump located at a different level.

Abstract: A semiconductor package includes a package substrate, an encapsulation structure stacked on the package substrate, a plurality of conductive bumps disposed between the package substrate and the encapsulation structure, and an adhesive layer attaching the package substrate and the encapsulation structure to each other. The encapsulation structure includes a sealing member having an upper surface and a lower surface opposite to each other, a plurality of semiconductor chips sequentially arranged in the sealing member such that a front surface on which chip pads are formed faces the package substrate, and conductive wires extending from a lower surface of the sealing member to the chip pads of the plurality of semiconductor chips. The plurality of conductive bumps are disposed between the conductive wires and substrate pads of the package substrate.

Abstract: A semiconductor package includes a redistribution wiring layer having redistribution wirings stacked in at least two levels; a first semiconductor chip arranged on the redistribution wiring layer; a plurality of second semiconductor chips arranged on the first semiconductor chip; first conductive wires electrically connecting first chip pads of the first semiconductor chip and the redistribution wirings of the redistribution wiring layer; second conductive wires electrically connecting second chip pads of the plurality of second semiconductor chips and the redistribution wirings of the redistribution wiring layer; and a sealing unit disposed on the redistribution wiring layer.

Abstract: A semiconductor package includes a first semiconductor chip, a lower redistribution structure electrically connected to the first semiconductor chip, an upper redistribution structure on the first semiconductor chip, a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure, and a first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure to dissipate heat of the first semiconductor chip.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.