Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

Abstract: An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.

Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

Abstract: A logic device includes a substrate; at least one first insulating layer on the substrate; a second insulating layer on the at least one first insulating layer; and a capacitor portion in the at least one first insulating layer and the second insulating layer, wherein the at least one first insulating layer includes a plurality of through-holes, the capacitor portion includes a capacitor structure including a lower electrode, a dielectric film, and an upper electrode, and the capacitor structure continuously extends along the inside of the plurality of through-holes and along an upper surface of the at least one first insulating layer around the plurality of through-holes.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a transistor provided on the first surface of the semiconductor substrate; a power rail provided on the first surface of the semiconductor substrate and electrically connected to the transistor; first and second lower interconnection lines provided on the second surface of the semiconductor substrate and spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate; a penetration via penetrating the semiconductor substrate and connecting a corresponding one of the first and second lower interconnection lines to the power rail; and a capacitor provided between and electrically connected to the first and second lower interconnection lines.

Abstract: An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.

Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

Abstract: Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer.

Abstract: Provided is a ramp tag capable of solving instability in translation rate resulting from poor compatibility between codons in a foreign gene and a host when expressing a recombinant protein in E. coli. Unlike the conventional codon optimization or codon deoptimization method for solving the problem of rare codons, the present invention increases an expression efficiency of a target protein by merely having the ramp tag be fused with a target gene or independently expressed, without changing the original codon sequence, thereby allowing tRNA to be reused. Thus, the present invention provides a novel method for increasing recombinant protein expression which is capable of reducing costs and time in comparison to the codon optimization method that artificially synthesizes DNA sequences. Therefore, it is expected that the method of the present invention will be able to be used in production of high value-added pharmaceuticals or industrial enzymes.

Abstract: Provided is a ramp tag capable of solving instability in translation rate resulting from poor compatibility between codons in a foreign gene and a host when expressing a recombinant protein in E. coli. Unlike the conventional codon optimization or codon deoptimization method for solving the problem of rare codons, the present invention increases an expression efficiency of a target protein by merely having the ramp tag be fused with a target gene or independently expressed, without changing the original codon sequence, thereby allowing tRNA to be reused. Thus, the present invention provides a novel method for increasing recombinant protein expression which is capable of reducing costs and time in comparison to the codon optimization method that artificially synthesizes DNA sequences. Therefore, it is expected that the method of the present invention will be able to be used in production of high value-added pharmaceuticals or industrial enzymes.