Patents by Inventor Wonjin Jang

Wonjin Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEU tolerant arbiter
    Patent number: 7999567
    Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 16, 2011
    Assignee: California Institute of Technology
    Inventors: Wonjin Jang, Christopher D. Moore, Alain J. Martin
  • SEU TOLERANT ARBITER
    Publication number: 20100176841
    Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 15, 2010
    Applicant: California Institute of Technology
    Inventors: Wonjin Jang, Christopher D. Moore, Alain J. Martin
  • Method and apparatus for providing SEU-tolerant circuits
    Patent number: 7721183
    Abstract: The invention provides circuits that are tolerant to soft errors, such as a single event upset (SEU). The circuits have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by an SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay-insensitive (QDI) asynchronous circuits.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 18, 2010
    Assignee: California Institute of Technology
    Inventors: Alain J. Martin, Wonjin Jang, Mika Nystroem
  • Duplicated double checking production rule set for fault-tolerant electronics
    Patent number: 7301362
    Abstract: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: November 27, 2007
    Assignee: California Institute of Technology
    Inventors: Wonjin Jang, Alain J. Martin, Mika Nystroem, Jonathan A. Dama
  • Duplicated double checking production rule set for fault-tolerant electronics
    Publication number: 20070016823
    Abstract: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.
    Type: Application
    Filed: March 14, 2006
    Publication date: January 18, 2007
    Applicant: California Institute of Technology
    Inventors: Wonjin Jang, Alain Martin, Mika Nystroem, Jonathan Dama
  • SEU-tolerant QDI circuits
    Publication number: 20060090099
    Abstract: The invention provides circuits that are tolerant to soft errors, such as a single event upset (SEU). The circuits may have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by and SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay-insensitive (QDI) asynchronous circuits.
    Type: Application
    Filed: August 30, 2005
    Publication date: April 27, 2006
    Inventors: Alain Martin, Wonjin Jang, Mika Nystroem