Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure provides intelligent services based on a variety of technologies, such as a smart home, a smart building, a smart city, a smart car, a connected car, a health care, a digital education, a smart retail, security and safety services. An apparatus and method for executing a task of an electronic device are provided. The apparatus includes a communication interface configured to receive state information associated with the electronic device from the electronic device, and a processor configured to determine whether to execute a specific task in the electronic device or a mobile terminal based on the state information about the electronic device and state information about the mobile terminal, and to indicate a result of the determination to the electronic device through the communication interface.

Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure provides intelligent services based on a variety of technologies, such as a smart home, a smart building, a smart city, a smart car, a connected car, a health care, a digital education, a smart retail, security and safety services. An apparatus and method for executing a task of an electronic device are provided. The apparatus includes a communication interface configured to receive state information associated with the electronic device from the electronic device, and a processor configured to determine whether to execute a specific task in the electronic device or a mobile terminal based on the state information about the electronic device and state information about the mobile terminal, and to indicate a result of the determination to the electronic device through the communication interface.

Abstract: A backlight assembly includes a light source, a circuit board on which the light source is disposed, a light guide plate having a light incident surface and a light emitting surface, a bottom case accommodating the light guide plate, a fixing frame coupled to the bottom case and fixing the circuit board, and a heat dissipation apparatus disposed between the light source and the light guide plate and including a light-transmitting unit that transmits light.

Abstract: A 3D image sensor module includes an image sensor including a plurality of color pixels and a plurality of infrared pixels, and a variable filter suitable for selectively filtering visible rays or infrared rays from light, which is incident on the image sensor, in a time-division way.

Abstract: A roller for a belt conveyer. A roller tube has an engraved groove for indicating the degree to which the surface of the roller is abraded. A shaft reinforcement member is provided in one end of the roller tube, connected to a shaft disposed inside the roller tube, and rotatably coupled to the belt conveyor. A dustproof cover closes one end of the roller tube, and the shaft reinforcement member extends through the dustproof cover. A bearing housing is fitted into the dustproof cover, with a bearing thereof being rotatably coupled to the outer circumference of the shaft reinforcement member. A flat spring is fitted into the bearing housing, and elastically supports one surface of the bearing, thereby controlling expansion or contraction of the bearing. An end cap is fixedly coupled to an outer surface of the dustproof cover in order to block impurities from entering the roller.

Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Abstract: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: A prefabricated windows and doors system includes a window frame including upper and lower frame, a window holder suspended from the upper frame, a window support slidably inserted into the lower guide recess to support a roller, which is rotatable, on the rail, and a window coupled to the window holder and the window support, and being attachable to or removable from the window holder and the window support. The upper frame has an upper guide recess, and the lower frame contains a stepped portion to have a staircase shape and contains a lower guide recess on a sidewall of the stepped portion. A guide bar extended in a sliding direction of the window may be further installed in the upper guide recess. A suspension portion of the window holder may have a ring shape surrounding the guide bar.

Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Abstract: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Abstract: A semiconductor structure includes a material layer on a substrate and to be patterned, an amorphous carbon layer on the material layer to be patterned, an N-free anti-reflective layer on the amorphous carbon layer, and a photoresist layer on the N-free anti-reflective layer. The N-free anti-reflective layer contains SiCXOYHZ as a main element. Related methods of patterning semiconductor structures also are provided.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Abstract: Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

Abstract: A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate, forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.