Abstract: Provided is an optical proximity correction (OPC) method including: receiving a design layout including a jumper via pattern connecting a first via pattern with a second via pattern, the first via pattern and the second via pattern each connecting different metal layers; setting the first via pattern as a hidden target that does not undergo OPC, setting the second via pattern as a real target that undergoes OPC, and performing first OPC; performing mask rule check (MRC) or optical rule check (ORC) on a result of the first OPC; setting the first via pattern as the real target that undergoes OPC, setting the second via pattern as the hidden target that does not undergo OPC, and performing second OPC; merging the result of the first OPC with a result of the second OPC; and performing the MRC or the ORC on a result of the merge.

Abstract: A method of manufacturing a semiconductor chip includes designing a layout for a semiconductor chip, performing an optical proximity correction (OPC) on the layout, manufacturing a mask after performing the OPC, and manufacturing the semiconductor chip using the mask, wherein a plurality of OPC shapes corresponding to a rectangular pattern of the mask are included in the mask and at least one of the plurality of OPC shapes includes a multi-edge corner rounding OPC shape.

Abstract: A photomask for a photolithography process includes a mask substrate, a reflective multilayer on the mask substrate, and a light absorber pattern on the reflective multilayer and having hole patterns, wherein the hole patterns include a main hole pattern for pattern transfer onto a wafer, first sub-resolution assist feature (SRAF) hole patterns arranged at regular intervals to provide honeycomb lattices in a first region centered around the main hole pattern and having a first pitch less than or equal to a diffraction limit in the photolithography process, and second SRAF hole patterns arranged at regular intervals to surround the main hole pattern and the first SRAF patterns and providing honeycomb lattices in a second region centered around the main hole pattern and surrounding the first region, the second SRAF hole patterns being arranged with a second pitch less than or equal to the diffraction limit in the photolithography process.

Abstract: A method of manufacturing a semiconductor chip includes designing a layout for a semiconductor chip, performing an optical proximity correction (OPC) on the layout, manufacturing a mask after performing the OPC, and manufacturing the semiconductor chip using the mask, wherein a plurality of OPC shapes corresponding to a rectangular pattern of the mask are included in the mask and at least one of the plurality of OPC shapes includes a multi-edge corner rounding OPC shape.