Patents by Inventor Won Kyu Han

Won Kyu Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145388
    Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Won Kyu HAN, Myeongsoo LEE, Rakhwan KIM, Woojin JANG
  • Patent number: 11928903
    Abstract: There is provided a method for providing driver's driving information of a user terminal device, including accessing a driving information providing server storing data generated in a driving recording device for a vehicle, receiving driving record data including event record data corresponding to a driving-related event of a driver from the driving information providing server, and displaying a driving-related event occurrence location on a map using the received driving record data. The driving-related event may include at least two or more of a lane departure event, a forward collision possibility event, a rear side collision possibility event, a sudden deceleration event, a sudden acceleration event, a sudden stop event, a sudden start event, and a speeding event.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 12, 2024
    Assignee: THINKWARE CORPORATION
    Inventors: Min Suk Kang, Won Jun Heo, Seung Yo Jang, Youn Joo Shin, Tae Kyu Han
  • Patent number: 11908798
    Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Kyu Han, Myeongsoo Lee, Rakhwan Kim, Woojin Jang
  • Publication number: 20220199526
    Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.
    Type: Application
    Filed: August 19, 2021
    Publication date: June 23, 2022
    Inventors: Won Kyu Han, Myeongsoo Lee, Rakhwan Kim, Woojin Jang
  • Publication number: 20120074575
    Abstract: A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 29, 2012
    Applicants: IUCF-HYU (Industry-Univeristy Cooperation Foundation Hanyang University), Hynix Semiconductor Inc.
    Inventors: Seung Jin YEOM, Jae Hong KIM, Sung Goon KANG, Won Kyu HAN
  • Patent number: 8088687
    Abstract: A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 3, 2012
    Assignees: Hynix Semiconductor Inc., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Seung Jin Yeom, Jae Hong Kim, Sung Goon Kang, Won Kyu Han
  • Publication number: 20110057316
    Abstract: A copper wiring of a semiconductor device is which is resistant to unwanted diffusion of copper from away from the copper wiring is presented. The copper wiring includes an interlayer dielectric, a self-assembly monolayer, a plurality of catalyst particles, a metal layer, and a copper layer. The interlayer dielectric on the semiconductor substrate has a wiring forming region. The self-assembly monolayer is the wiring forming region. The plurality of catalyst particles are adsorbed onto the surface of the self-assembly monolayer. The metal layer is formed on the self-assembly monolayer which has the adsorbed catalyst particles such that the metal layer serves as both a seed layer and as a diffusion barrier. The copper layer substantially fills in the wiring forming region.
    Type: Application
    Filed: December 10, 2009
    Publication date: March 10, 2011
    Applicants: Hynix Semiconductor Inc., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Jae Hong KIM, Sung Goon KANG, Won Kyu HAN, Soo Ho PARK
  • Publication number: 20100244253
    Abstract: A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.
    Type: Application
    Filed: June 25, 2009
    Publication date: September 30, 2010
    Inventors: Seung Jin YEOM, Jae Hong KIM, Sung Goon KANG, Won Kyu HAN