Patents by Inventor Won-Sang Song
Won-Sang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11911153Abstract: The present invention provides a device for measuring biological information including a sensor array, wherein the sensor array includes a plurality of sensors that are either sensors for amplifying photoreactivity or sensors forming an island network connected by a plurality of multi-channels and, in the device, the average value of biological information about the skin tissues is measured based on values output from the sensor array, and a method of measuring biological information using the device.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignees: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY, Korea Electronics Technology InstituteInventors: Sun Kook Kim, Sung Ho Lee, Min Goo Lee, Hyuk Sang Jung, Min Jung Kim, Young Ki Hong, Won Geun Song
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Patent number: 7951712Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: September 9, 2009Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Publication number: 20100003814Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: September 9, 2009Publication date: January 7, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7605472Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: February 15, 2007Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Publication number: 20070138642Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: February 15, 2007Publication date: June 21, 2007Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7205666Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: March 3, 2006Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Publication number: 20060163736Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: March 3, 2006Publication date: July 27, 2006Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7037835Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: December 23, 2003Date of Patent: May 2, 2006Assignee: Samsung Elecrtonics, Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 6881630Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.Type: GrantFiled: April 30, 2003Date of Patent: April 19, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
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Patent number: 6842028Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: GrantFiled: January 27, 2004Date of Patent: January 11, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Publication number: 20040189338Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: ApplicationFiled: January 27, 2004Publication date: September 30, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Publication number: 20040135261Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 6740587Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.Type: GrantFiled: September 12, 2001Date of Patent: May 25, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jeong-Hwan Yang, In-Sun Park, Byoung-Moon Yoon
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Patent number: 6693446Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.Type: GrantFiled: April 1, 2002Date of Patent: February 17, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Patent number: 6690187Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: GrantFiled: April 1, 2002Date of Patent: February 10, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Patent number: 6645866Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.Type: GrantFiled: December 16, 2002Date of Patent: November 11, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Kyung-won Park, Jung-woo Park, Won-sang Song
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Publication number: 20030197224Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.Type: ApplicationFiled: April 30, 2003Publication date: October 23, 2003Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
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Patent number: 6580134Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.Type: GrantFiled: October 6, 2000Date of Patent: June 17, 2003Assignee: Samsung Electronics, Co., Ltd.Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
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Publication number: 20030104677Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.Type: ApplicationFiled: December 16, 2002Publication date: June 5, 2003Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Tai-Su Park, Kyung-Won Park, Jung-Woo Park, Won-Sang Song
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Publication number: 20030020497Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.Type: ApplicationFiled: April 1, 2002Publication date: January 30, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park