Patents by Inventor Wonseb Jeong
Wonseb Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983115Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.Type: GrantFiled: February 8, 2023Date of Patent: May 14, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongho Lee, Heehyun Nam, Jaeho Shin, Hyodeok Shin, Younggeon Yoo, Younho Jeon, Wonseb Jeong, Ipoom Jeong, Hyeokjun Choe
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Publication number: 20240103755Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Wonseb JEONG, Hongju KAL, Won Woo RO, Seokmin LEE, Gun KO
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Publication number: 20240053917Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Wonseb Jeong, Yang Seok Ki, Jungmin Seo, Beomkyu Shin, Sangoak Woo, Younggeon Yoo, Chanho Yoon, Myungjune Jung
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Patent number: 11899970Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.Type: GrantFiled: May 11, 2022Date of Patent: February 13, 2024Inventors: Wonseb Jeong, Hee Hyun Nam, Younggeon Yoo, Jeongho Lee, Younho Jeon, Ipoom Jeong, Chanho Yoon
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Patent number: 11880590Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.Type: GrantFiled: June 10, 2022Date of Patent: January 23, 2024Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Wonseb Jeong, Hongju Kal, Won Woo Ro, Seokmin Lee, Gun Ko
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Patent number: 11853215Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.Type: GrantFiled: August 23, 2021Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseb Jeong, Heehyun Nam, Jeongho Lee
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Publication number: 20230384960Abstract: Disclosed are a storage system and an operation method therefor. The storage system includes: a host system; and a plurality of storage sets configured to interface with the host system. At least one of the plurality of storage sets includes: a first memory region; a second memory region; and a third memory region, and the at least one of the plurality of storage sets is configured to move data stored in the third memory region to a selected memory region among the first memory region and the second memory region based on a data access feature.Type: ApplicationFiled: April 28, 2023Publication date: November 30, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseb JEONG, SOO-YOUNG Ji
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Patent number: 11822813Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.Type: GrantFiled: February 25, 2022Date of Patent: November 21, 2023Inventors: Wonseb Jeong, Yang Seok Ki, Jungmin Seo, Beomkyu Shin, Sangoak Woo, Younggeon Yoo, Chanho Yoon, Myungjune Jung
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Patent number: 11741034Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.Type: GrantFiled: July 7, 2021Date of Patent: August 29, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heehyun Nam, Jeongho Lee, Wonseb Jeong, Ipoom Jeong, Hyeokjun Choe
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Publication number: 20230266917Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.Type: ApplicationFiled: June 28, 2022Publication date: August 24, 2023Inventors: HYEOKJUN CHOE, JEONGHO LEE, YOUNGGEON YOO, WONSEB JEONG
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Publication number: 20230205449Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.Type: ApplicationFiled: February 25, 2022Publication date: June 29, 2023Inventors: WONSEB JEONG, YANG SEOK KI, JUNGMIN SEO, BEOMKYU SHIN, SANGOAK WOO, YOUNGGEON YOO, CHANHO YOON, MYUNGJUNE JUNG
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Publication number: 20230185717Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongho LEE, Heehyun Nam, Jaeho Shin, Hyodeok Shin, Younggeon Yoo, Younho Jeon, Wonseb Jeong, Ipoom Jeong, Hyeokjun Choe
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Publication number: 20230100573Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.Type: ApplicationFiled: May 11, 2022Publication date: March 30, 2023Inventors: WONSEB JEONG, HEE HYUN NAM, YOUNGGEON YOO, JEONGHO LEE, YOUNHO JEON, IPOOM JEONG, CHANHO YOON
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Patent number: 11586543Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.Type: GrantFiled: July 20, 2021Date of Patent: February 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongho Lee, Heehyun Nam, Jaeho Shin, Hyodeok Shin, Younggeon Yoo, Younho Jeon, Wonseb Jeong, Ipoom Jeong, Hyeokjun Choe
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Publication number: 20220398032Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.Type: ApplicationFiled: June 10, 2022Publication date: December 15, 2022Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Wonseb JEONG, Hongju KAL, Won Woo RO, Seokmin LEE, Gun KO
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Publication number: 20220164286Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.Type: ApplicationFiled: August 23, 2021Publication date: May 26, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseb JEONG, Heehyun NAM, Jeongho LEE
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Publication number: 20220147476Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.Type: ApplicationFiled: July 7, 2021Publication date: May 12, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heehyun NAM, Jeongho LEE, Wonseb JEONG, Ipoom JEONG, Hyeokjun CHOE
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Publication number: 20220121574Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.Type: ApplicationFiled: July 20, 2021Publication date: April 21, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongho LEE, Heehyun Nam, Jaeho Shin, Hyodeok Shin, Younggeon Yoo, Younho Jeon, Wonseb Jeong, Ipoom Jeong, Hyeokjun Choe
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Patent number: 9304965Abstract: According to one embodiment, a scheduling method for load balancing in an electronic device such as a server when performing multiple transcoding operations includes performing a first transcoding operation in order to transmit at least one moving image file to a first terminal. The server receives a request from a second terminal to transmit at least one moving image file while performing the first transcoding. The server performs a second transcoding operation in order to transmit the requested moving image file to the second terminal. The server monitors output frame rates of the first transcoding operation and the second transcoding operation, to control the output frame rates.Type: GrantFiled: March 21, 2013Date of Patent: April 5, 2016Assignees: Samsung Electronics Co., Ltd, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Jae-Ho Kim, Sun-Mi Kim, Won Woo Ro, Changmin Lee, Wonseb Jeong, Jin-Won Kim
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Publication number: 20130254386Abstract: According to one embodiment, a scheduling method for load balancing in an electronic device such as a server when performing multiple transcoding operations includes performing a first transcoding operation in order to transmit at least one moving image file to a first terminal. The server receives a request from a second terminal to transmit at least one moving image file while performing the first transcoding. The server performs a second transcoding operation in order to transmit the requested moving image file to the second terminal. The server monitors output frame rates of the first transcoding operation and the second transcoding operation, to control the output frame rates.Type: ApplicationFiled: March 21, 2013Publication date: September 26, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Kim, Sun-Mi Kim, Won Woo Ro, Changmin Lee, Wonseb Jeong, Jin-Won Kim