Patents by Inventor Won-Seok Jung
Won-Seok Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145118Abstract: A transparent conductor according to an exemplary embodiment of the present invention includes a transparent substrate, and a transparent conductive pattern formed on the transparent substrate, and the transparent conductor includes a nanostructure on an upper surface of at least one of the transparent substrate and the transparent conductive pattern.Type: ApplicationFiled: March 17, 2021Publication date: May 2, 2024Inventors: Dae-Guen CHOI, Hyuk Jun KANG, Ji Hye LEE, Junhyuk CHOI, Won Seok CHANG, Joo Yun JUNG, Jun-ho JEONG
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Patent number: 11967076Abstract: A computing device includes at least one memory, and at least one processor configured to generate, based on first analysis on a pathological slide image, first biomarker expression information, generate, based on a user input for updating at least some of results of the first analysis, second biomarker expression information about the pathological slide image, and control a display device to output a report including medical information about at least some regions included in the pathological slide image, based on at least one of the first biomarker expression information or the second biomarker expression information.Type: GrantFiled: March 17, 2023Date of Patent: April 23, 2024Assignee: LUNIT INC.Inventors: Jeong Seok Kang, Dong Geun Yoo, Soo Ick Cho, Won Kyung Jung
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Publication number: 20240091767Abstract: A gene amplification chip includes a chamber layer, a cover layer, a bottom layer, an inlet, and an outlet. The chamber layer has a first passage and through holes which are formed on one side of the first passage. The cover layer is disposed on one side of the chamber layer and has a cover channel formed to communicate with the first passage and the through holes, wherein the cover channel, the first passage and the through holes allow passage of liquids in a divided manner. The bottom layer is disposed on another side of the chamber layer and has a bottom channel formed to communicate with the first passage and the through holes. The inlet is formed in the cover layer and communicates with the cover channel. The outlet communicates with any one of the cover channel and the bottom channel.Type: ApplicationFiled: December 15, 2022Publication date: March 21, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: Jae Hong LEE, Won Jong JUNG, Kak NAMKOONG, Hyeong Seok JANG, Jin Ha KIM, Hyung Jun YOUN
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Patent number: 11398054Abstract: According to an embodiment, a device for detecting fog on a road comprises an imaging device installed to capture a two-way road and capturing a fog on the two-way road, a network configuring device provided under the imaging device and transmitting an image captured by the imaging device, a fog monitoring device receiving the image from the network configuring device, analyzing the image to thereby detect the fog, and outputting an alert per predetermined crisis level, and a display device displaying the alert output from the fog monitoring device and transmitting the alert via a wired or wireless network.Type: GrantFiled: October 6, 2020Date of Patent: July 26, 2022Inventors: Kyung Won Kim, Won Seok Jung
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Publication number: 20220028118Abstract: According to an embodiment, a device for detecting fog on a road comprises an imaging device installed to capture a two-way road and capturing a fog on the two-way road, a network configuring device provided under the imaging device and transmitting an image captured by the imaging device, a fog monitoring device receiving the image from the network configuring device, analyzing the image to thereby detect the fog, and outputting an alert per predetermined crisis level, and a display device displaying the alert output from the fog monitoring device and transmitting the alert via a wired or wireless network.Type: ApplicationFiled: October 6, 2020Publication date: January 27, 2022Inventors: Kyung Won KIM, Won Seok JUNG
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Patent number: 10490566Abstract: A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.Type: GrantFiled: February 12, 2016Date of Patent: November 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Seok Jung, Brad H. Lee, Sang Woo Jin
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Patent number: 10297451Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.Type: GrantFiled: July 10, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Seok Jung, Joon Hee Lee, Keon Soo Kim, Sun Yeong Lee
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Patent number: 9955112Abstract: Provided is a digital-image transmission apparatus including a transmitting unit connected to a host device and a receiving unit connected to a display device. The transmitting unit includes a host-side additional-communication control unit that controls additional communication for digital image transmission. The host-side additional-5 communication control unit performs communication with an external device to diagnose an operation state of the transmitting unit, transmit a diagnosis result to the external device, and control an operation of the transmitting unit.Type: GrantFiled: July 8, 2014Date of Patent: April 24, 2018Assignee: OPTICS CO, LTD.Inventors: Won Seok Jung, Jae Chul Ko, Doo Soo Ha, Yoo Sung Tak
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Publication number: 20170309486Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Won Seok JUNG, Joon Hee LEE, Keon Soo KIM, Sun Yeong LEE
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Patent number: 9780113Abstract: A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.Type: GrantFiled: December 9, 2015Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jiwoon Im, Kwangchul Park, Jiyoun Seo, Jongmyeong Lee, Kyung-Tae Jang, Byungho Chun, Won-Seok Jung, Jongwan Choi, Tae-Jong Han
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Patent number: 9748257Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.Type: GrantFiled: December 8, 2015Date of Patent: August 29, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehan Lee, Won-Seok Jung, Kyungjoong Joo
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Patent number: 9735014Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.Type: GrantFiled: March 9, 2015Date of Patent: August 15, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Seok Jung, Joon Hee Lee, Keon Soo Kim, Sun Yeong Lee
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Patent number: 9698158Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.Type: GrantFiled: August 26, 2016Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Seok Jung, Changseok Kang, Seungwoo Paek, Inseok Yang, Kyungjoong Joo
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Patent number: 9612990Abstract: A dual mode display-port connector including a host-side auxiliary interface, a display-side auxiliary interface, and a cable. Each of the host-side auxiliary interface and the display-side auxiliary interface includes a bi-directional converter and a direct-current (DC) balancing codec. The bi-directional converter converts differential auxiliary signals received via one side thereof into a single auxiliary signal and a single auxiliary signal received via another side thereof into differential auxiliary signals. The direct-current (DC) balancing codec performs DC balancing encoding on a single auxiliary signal received via one side thereof, and decodes an encoded single auxiliary signal obtained through an encoding process and received via another side thereof.Type: GrantFiled: July 2, 2014Date of Patent: April 4, 2017Assignee: OPTICIS CO., LTD.Inventors: Dong Pyeong Yang, Won Seok Jung, Won Gil Byun
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Publication number: 20160365356Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Won-Seok JUNG, Changseok KANG, Seungwoo PAEK, Inseok YANG, Kyungjoong JOO
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Publication number: 20160343725Abstract: A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.Type: ApplicationFiled: February 12, 2016Publication date: November 24, 2016Inventors: Won Seok JUNG, Brad H. LEE, Sang Woo JIN
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Patent number: 9484355Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.Type: GrantFiled: July 16, 2015Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Seok Jung, Changseok Kang, SeungWoo Paek, Inseok Yang, Kyungjoong Joo
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Patent number: 9431418Abstract: A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.Type: GrantFiled: April 28, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Jung, Chang-Seok Kang, Min-Yong Lee, Sang-Woo Jin
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Publication number: 20160233232Abstract: A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.Type: ApplicationFiled: December 9, 2015Publication date: August 11, 2016Inventors: Jiwoon IM, Kwangchul PARK, Jiyoun SEO, Jongmyeong LEE, Kyung-Tae JANG, Byungho CHUN, Won-Seok JUNG, Jongwan CHOI, Tae-Jong HAN
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Patent number: 9373635Abstract: A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.Type: GrantFiled: July 16, 2015Date of Patent: June 21, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Jung, Youngok Kim, Jihye Kim, Kyungjoong Joo