Patents by Inventor Won-Seok Yoo

Won-Seok Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967076
    Abstract: A computing device includes at least one memory, and at least one processor configured to generate, based on first analysis on a pathological slide image, first biomarker expression information, generate, based on a user input for updating at least some of results of the first analysis, second biomarker expression information about the pathological slide image, and control a display device to output a report including medical information about at least some regions included in the pathological slide image, based on at least one of the first biomarker expression information or the second biomarker expression information.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 23, 2024
    Assignee: LUNIT INC.
    Inventors: Jeong Seok Kang, Dong Geun Yoo, Soo Ick Cho, Won Kyung Jung
  • Publication number: 20230284439
    Abstract: A semiconductor memory device includes a substrate including a trench and a contact recess, a direct contact placed inside the trench and having a width smaller than a width of the trench, a bit line structure placed on the direct contact and having a width smaller than the width of the trench, a spacer structure placed on side surfaces of the direct contact and the bit line structure, and a buried contact spaced apart from the direct contact and the bit line structure by the spacer structure and filling the contact recess. The spacer structure includes an oxide film placed between the direct contact and the buried contact inside the trench, a seed layer placed on the oxide film inside the trench between the direct contact and the buried contact, and a bulk layer filling the trench on the seed layer and including silicon nitride. The seed layer includes carbon.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Chang Woo SEO, Hyun-Chul SHIM, Da In LEE, Su Youn SONG, Jeong Eun SONG, Won Seok YOO
  • Patent number: 11468919
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Jin Park, Won Seok Yoo, Keun Nam Kim, Hyo-Sub Kim, So Hyun Park, In Kyoung Heo, Yoo Sang Hwang
  • Patent number: 11147704
    Abstract: A cervicothoracic spine restorator is disclosed. In the cervicothoracic spine restorator, a fixing structure is further included, such that relaxation of muscles such as pectoralis major muscle, pectoralis minor muscle, rectus abdominis muscle, and trapezius muscle or latissimus dorsi muscle can be easily performed. Further, the blood vessel may be expanded and the blood may be supplied smoothly to the head. This may help recovery and correction during a short correction period. There is an advantage that a separate correction mechanism, which is used for spine correction such as a abdomen band, is unnecessary.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 19, 2021
    Inventors: Won Seok Yoo, Mahn June Hahn
  • Publication number: 20210035613
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: February 4, 2021
    Inventors: Tae Jin PARK, Won Seok Yoo, Keun Nam Kim, Hyo-Sub Kim, So Hyun Park, In Kyoung Heo, Yoo Sang Hwang
  • Publication number: 20190262162
    Abstract: A cervicothoracic spine restorator is disclosed. In the cervicothoracic spine restorator, a fixing structure is further included, such that relaxation of muscles such as pectoralis major muscle, pectoralis minor muscle, rectus abdominis muscle, and trapezius muscle or latissimus dorsi muscle can be easily performed. Further, the blood vessel may be expanded and the blood may be supplied smoothly to the head. This may help recovery and correction during a short correction period. There is an advantage that a separate correction mechanism, which is used for spine correction such as a abdomen band, is unnecessary.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 29, 2019
    Inventors: Won Seok YOO, Mahn June HAHN
  • Patent number: 9202844
    Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jong Han, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
  • Patent number: 9153590
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jin Lim, Won-Seok Yoo, Seok-Woo Nam
  • Patent number: 9041122
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seok Yoo, Young-seok Kim, Han-jin Lim, Jeon-Il Lee
  • Publication number: 20150124521
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.
    Type: Application
    Filed: June 5, 2014
    Publication date: May 7, 2015
    Inventors: Han-Jin Lim, Won-Seok Yoo, Seok-Woo Nam
  • Publication number: 20150061136
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Application
    Filed: May 1, 2014
    Publication date: March 5, 2015
    Inventors: Won-seok YOO, Young-seok KIM, Han-jin LIM, Jeon-II LEE
  • Patent number: 8928152
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Publication number: 20140167288
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Publication number: 20140158964
    Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.
    Type: Application
    Filed: August 14, 2013
    Publication date: June 12, 2014
    Inventors: Jae-Jong HAN, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
  • Patent number: 8697570
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Publication number: 20110198758
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Application
    Filed: November 8, 2010
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Patent number: 7598141
    Abstract: A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hoon Lee, Sang-Jin Park, Won-Seok Yoo, Kong-Soo Lee
  • Patent number: 7592227
    Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sun Lee, Jai-Dong Lee, Bong-Hyun Kim, Man-Sug Kang, Jung-Hwan Kim, Hyun-Jin Shin, Won-Seok Yoo, Seung-Mok Shin
  • Publication number: 20070232396
    Abstract: An online game service system for randomly allocating game channels according to user behavior patterns includes a user behavior pattern database, a channel database, a channel server, and a game server so that users having the same or similar game behavior patterns may play games. The user behavior pattern database stores behavior pattern classification references and user game behavior patterns. The channel database stores a list of random channels and data on game rooms at the random channels. The channel server selects a random channel according to the user behavior pattern, provides data on game rooms generated in the selected random channel, and controls a user to enter a game room. The game server provides a game service to the users having entered game rooms, determines game behavior patterns of the users by using behavior pattern references, and stores the determined game behavior patterns in the user behavior pattern database.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 4, 2007
    Applicant: NHN CORPORATION
    Inventor: Won-Seok Yoo
  • Patent number: D636704
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: April 26, 2011
    Assignee: Daedong Industrial Co., Ltd.
    Inventors: Won Seok Yoo, Jung Lul Back, Soon Yeol Kim