Patents by Inventor Wonseop LEE
Wonseop LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974391Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.Type: GrantFiled: January 11, 2022Date of Patent: April 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongyoon Seo, Hwanwook Park, Dohyung Kim, Bora Kim, Seungyeong Lee, Wonseop Lee, Yunho Lee, Yejin Cho
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Publication number: 20230413424Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.Type: ApplicationFiled: August 31, 2023Publication date: December 21, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseop LEE, Hwanwook Park, Jeonghoon Baek, Dohyung Kim, Seunghee Mun, Dongyoon Seo, Jinoh Ahn
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Patent number: 11812547Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.Type: GrantFiled: June 24, 2021Date of Patent: November 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongyoon Seo, Sangkeun Kwak, Dohyung Kim, Kyeongseon Park, Hwanwook Park, Wonseop Lee, Daae Heo
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Patent number: 11785710Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.Type: GrantFiled: September 19, 2022Date of Patent: October 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseop Lee, Hwanwook Park, Jeonghoon Baek, Dohyung Kim, Seunghee Mun, Dongyoon Seo, Jinoh Ahn
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Publication number: 20230013064Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseop LEE, Hwanwook PARK, Jeonghoon BAEK, Dohyung KIM, Seunghee MUN, Dongyoon SEO, Jinoh AHN
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Publication number: 20220408550Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.Type: ApplicationFiled: January 11, 2022Publication date: December 22, 2022Inventors: Dongyoon SEO, Hwanwook PARK, Dohyung KIM, Bora KIM, Seungyeong LEE, Wonseop LEE, Yunho LEE, Yejin CHO
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Patent number: 11477880Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.Type: GrantFiled: June 3, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseop Lee, Hwanwook Park, Jeonghoon Baek, Dohyung Kim, Seunghee Mun, Dongyoon Seo, Jinoh Ahn
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Publication number: 20220159827Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.Type: ApplicationFiled: June 3, 2021Publication date: May 19, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseop LEE, Hwanwook PARK, Jeonghoon BAEK, Dohyung KIM, Seunghee MUN, Dongyoon SEO, Jinoh AHN
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Publication number: 20220070999Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.Type: ApplicationFiled: June 24, 2021Publication date: March 3, 2022Inventors: DONGYOON SEO, SANGKEUN KWAK, DOHYUNG KIM, KYEONGSEON PARK, HWANWOOK PARK, WONSEOP LEE, DAAE HEO
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Patent number: 10482642Abstract: A method for automatic garment fit customization is provided. The method comprising steps for generating a garment by creating two-dimensional (2D) panels, in which the garment comprises a plurality of garment landmarks (GLMs) and a plurality of garment landmark lines (GLLs), which are key locations and lines on a surface of the garment, simulating draping of the garment on a reference body, where the reference body comprises body landmarks (BLMs) and body landmark lines (BLLs), performing a fit evaluation and calculating misfit measures comprising landmark (LM) misfits, landmark line (LL) misfits, and circumferential misfits, performing a fit adjustment for panel alteration operations modifying some of the 2D panels based on the fit evaluation, performing draping simulation with the modified 2D panels, and repeating until the misfit measures fall within a predetermined criterion and determining customized 2D panels that fit the reference body.Type: GrantFiled: July 5, 2017Date of Patent: November 19, 2019Assignee: TG3D STUDIO.INC.Inventors: Bong Ouk Choi, Wonseop Lee
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Publication number: 20180012385Abstract: A method for automatic garment fit customization is provided. The method comprising steps for generating a garment by creating two-dimensional (2D) panels, in which the garment comprises a plurality of garment landmarks (GLMs) and a plurality of garment landmark lines (GLLs), which are key locations and lines on a surface of the garment, simulating draping of the garment on a reference body, where the reference body comprises body landmarks (BLMs) and body landmark lines (BLLs), performing a fit evaluation and calculating misfit measures comprising landmark (LM) misfits, landmark line (LL) misfits, and circumferential misfits, performing a fit adjustment for panel alteration operations modifying some of the 2D panels based on the fit evaluation, performing draping simulation with the modified 2D panels, and repeating until the misfit measures fall within a predetermined criterion and determining customized 2D panels that fit the reference body.Type: ApplicationFiled: July 5, 2017Publication date: January 11, 2018Inventors: Bong Ouk CHOI, Wonseop LEE