Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A circuit board according to an embodiment includes an insulating layer; a second outer circuit pattern disposed on an upper surface of the insulating layer; and a via disposed in the insulating layer and connected to the second outer circuit pattern; wherein the second outer circuit pattern includes: a first pattern embedded in the insulating layer and having a first width; and a second pattern protruding on the upper surface of the insulating layer, having a second width greater than the first width, and connected to the first pattern through the via.

Abstract: A circuit board according to an embodiment includes an insulating layer; a second outer circuit pattern disposed on an upper surface of the insulating layer; and a via disposed in the insulating layer and connected to the second outer circuit pattern; wherein the second outer circuit pattern includes: a first pattern embedded in the insulating layer and having a first width; and a second pattern protruding on the upper surface of the insulating layer, having a second width greater than the first width, and connected to the first pattern through the via.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first circuit pattern buried in a lower region of the first insulating layer and including a first via pad; a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad; a third circuit pattern buried in an upper region of the second insulating layer and including a third via pad; a first via disposed in the first insulating layer and connecting the first via pad and the second via pad; and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and wherein at least one of an upper surface and a lower surface of the second via includes a convex portion in an upward or downward direction.

Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A semiconductor package according to an embodiment includes a first substrate layer; and a second substrate layer disposed on the first substrate layer, wherein the first substrate layer includes at least one first insulating layer; a first circuit pattern disposed on the first insulating layer; and a first via passing through the first insulating layer and connected to the first circuit pattern, wherein the second substrate layer includes a second insulating layer disposed on the first insulating layer; a second circuit pattern disposed on the second insulating layer; and a second via passing through the second insulating layer and connected to the second circuit pattern, wherein the first insulating layer and the second insulating layer include different insulating materials and wherein a width of the first via is different from a width of the second via.

Abstract: The present disclosure provides a method of preparing graphene quantum dots by intercalation of graphite nanoparticles and continuous exfoliation in an aqueous solution. The preparation method has a short process time and uses graphite nanoparticles of several nm as a reactant. Thus, graphene quantum dots prepared by the preparation method are uniform in size and shape with minimized defects and improved electrical properties.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first circuit pattern buried in a lower region of the first insulating layer and including a first via pad; a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad; a third circuit pattern buried in an upper region of the second insulating layer and including a third via pad; a first via disposed in the first insulating layer and connecting the first via pad and the second via pad; and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and wherein at least one of an upper surface and a lower surface of the second via includes a convex portion in an upward or downward direction.

Abstract: A circuit board according to an embodiment includes an insulating layer; a second outer circuit pattern disposed on an upper surface of the insulating layer; and a via disposed in the insulating layer and connected to the second outer circuit pattern; wherein the second outer circuit pattern includes: a first pattern embedded in the insulating layer and having a first width; and a second pattern protruding on the upper surface of the insulating layer, having a second width greater than the first width, and connected to the first pattern through the via.

Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

Abstract: A system for sensing and notifying material leakage includes a material leakage sensor provided as plural ones within a specific facility and configured to sense whether a material including a liquid or a gas leaks to the outside of a joint portion or an opening/closing portion of the equipment located inside or outside of the specific facility; and a controller configured to receive sensing information sensed by the material leakage sensor and transmit a material leakage notification to a security company device through a wireless communication module based on the sensing information. The security company device is a device of a security company in charge of security or guard for the specific facility.

Abstract: The present disclosure provides a method of preparing graphene quantum dots by intercalation of graphite nanoparticles and continuous exfoliation in an aqueous solution. The preparation method has a short process time and uses graphite nanoparticles of several nm as a reactant. Thus, graphene quantum dots prepared by the preparation method are uniform in size and shape with minimized defects and improved electrical properties.

Abstract: A printed circuit board according to an embodiment comprises: a first insulation layer; a plurality of first cavities formed in the central region of the first insulation layer; a plurality of second cavities formed in the outer region of the first insulation layer, excluding the central region; real dies respectively disposed in the plurality of first cavities; dummy dies respectively disposed in the plurality of second cavities; a second insulation layer formed on the first insulation layer and filling the first cavities and the second cavities; and a third insulation layer disposed beneath the first insulation layer, wherein the real dies comprise substantial driving elements and the dummy dies do not comprise the driving elements.

Abstract: A system for sensing and notifying material leakage includes a material leakage sensor provided as plural ones within a specific facility and configured to sense whether a material including a liquid or a gas leaks to the outside of a joint portion or an opening/closing portion of the equipment located inside or outside of the specific facility; and a controller configured to receive sensing information sensed by the material leakage sensor and transmit a material leakage notification to a security company device through a wireless communication module based on the sensing information. The security company device is a device of a security company in charge of security or guard for the specific facility.

Abstract: A printed circuit board according to an embodiment comprises: a first insulation layer; a plurality of first cavities formed in the central region of the first insulation layer; a plurality of second cavities formed in the outer region of the first insulation layer, excluding the central region; real dies respectively disposed in the plurality of first cavities; dummy dies respectively disposed in the plurality of second cavities; a second insulation layer formed on the first insulation layer and filling the first cavities and the second cavities; and a third insulation layer disposed beneath the first insulation layer, wherein the real dies comprise substantial driving elements and the dummy dies do not comprise the driving elements.

Abstract: A method for initializing a memory that is part of an electronic device, comprising: receiving a sequence for initializing the memory from an external booting device; and causing the memory to perform initialization by using a first command that is generated based on the sequence.

Abstract: Provided are a printed circuit board and a method of manufacturing the printed circuit board, the printed circuit board including: a first element and a second element; a first base substrate including an embedding part in which the first element is embedded and a cavity into which the second element is mounted; and a second base substrate bonded to one surface of the first base substrate and including a first via for the second element.