Patents by Inventor Won-Woong Chung

Won-Woong Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553449
    Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Hye Hwang, Youn-Joung Cho, Won-Woong Chung, Nam-Gun Kim, Kong-Soo Lee, Badro Im, Yoon-Chul Cho
  • Patent number: 10049882
    Abstract: A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 14, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DOW SILICONES CORPORATION
    Inventors: Won Woong Chung, Sun hye Hwang, Youn Joung Cho, Jung Sik Choi, Xiaobing Zhou, Brian David Rekken, Byung Keun Hwang, Michael David Telgenhoff
  • Publication number: 20180211842
    Abstract: A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 26, 2018
    Applicant: DOW CORNING CORPORATION
    Inventors: Won Woong CHUNG, Sun hye HWANG, Youn Joung CHO, Jung Sik CHOI, Xiaobing ZHOU, Brian David REKKEN, Byung Keun HWANG, Michael David TELGENHOFF
  • Patent number: 9991112
    Abstract: A method of forming a dielectric film includes providing a substrate in a chamber, and forming a silicon nitride film on the substrate using an atomic layer deposition (ALD) method in which a first gas including a silicon precursor containing hexachlorodisilazane (HCDZ) and a second gas containing a nitrogen ingredient are introduced into the chamber.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Woong Chung, Youn Joung Cho, Sun Hye Hwang
  • Publication number: 20180102260
    Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.
    Type: Application
    Filed: September 11, 2017
    Publication date: April 12, 2018
    Inventors: Sun-Hye HWANG, Youn-Joung CHO, Won-Woong CHUNG, Nam-Gun KIM, Kong-Soo LEE, Badro IM, Yoon-Chul CHO
  • Publication number: 20180090313
    Abstract: A method of forming a dielectric film includes providing a substrate in a chamber, and forming a silicon nitride film on the substrate using an atomic layer deposition (ALD) method in which a first gas including a silicon precursor containing hexachlorodisilazane (HCDZ) and a second gas containing a nitrogen ingredient are introduced into the chamber.
    Type: Application
    Filed: June 30, 2017
    Publication date: March 29, 2018
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: WON WOONG CHUNG, YOUN JOUNG CHO, SUN HYE HWANG
  • Patent number: 9812329
    Abstract: There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Woong Chung, Youn Joung Cho, Jung Sik Choi
  • Publication number: 20170170023
    Abstract: There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.
    Type: Application
    Filed: October 12, 2016
    Publication date: June 15, 2017
    Inventors: Won Woong CHUNG, Youn Joung CHO, Jung Sik CHOI
  • Publication number: 20160303620
    Abstract: An apparatus for manufacturing an electronic device, including a chamber; and a supply line supplying cleaning gas to an inside of the chamber, the apparatus cleaning the inside of the chamber using the cleaning gas including diatomic molecules that are heteronuclear molecules containing a halogen element, while the inside of the chamber is maintained at a temperature of about 400° C. to about 1000° C.
    Type: Application
    Filed: January 6, 2016
    Publication date: October 20, 2016
    Inventors: Do-hoon KIM, Won-woong CHUNG
  • Publication number: 20090095996
    Abstract: A semiconductor device includes a substrate including an active region, a first impurity region, second impurity regions, a word line and a bit line. The active region has end portions extending in a first direction and a central portion extending in a second direction inclined relative to the first direction. The first impurity region is disposed at the central portion, and the second impurity regions are disposed at the end portions. The word line extends in a third direction substantially perpendicular to the first direction. The bit line extends in the first direction. The bit line is electrically connected to the first impurity region. The second impurity regions may be symmetrical to each other centering adjacent two word lines and adjacent one bit line. The semiconductor device may have improved sensing margin by reducing the capacitance of the bit line.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Inventors: Won-Woong Chung, Young-Min Kang