Abstract: A method of processing an input signal of a portable device is provided, including collecting an input signal generated from at least one of an input unit and a touch screen; generating a preset repetitive input signal when the collected input signal corresponds to a preset condition input signal; and using an application that is currently activated based on the repetitive input signal.

Abstract: A mobile terminal and communication mode switching method is capable of efficiently managing a data connection to a network via a wireless link when the mobile terminal switches between a master operation mode and a slave operation mode. A communication mode switching method determines whether a request for a second mode communication session is detected while the mobile terminal is in a first mode communication session with a network via a first interface. The system and method initializes and activates a second interface when a request for a second mode communication session is detected. The system and method also synchronize the first interface and the second interface, re-register a Mobile Internet Protocol (MIP) with the network, acquire an IP address as a consequence of the re-registration of the MIP, and communicate data with the network using the acquired IP address.

Abstract: A method and system for notifying a first portable terminal regarding the absence of a second terminal in a Push-To-Talk (PTT) service. The system allows a first portable terminal user to transmit an absence notifying message to the second portable terminal user, and displays an absent state of the first portable terminal user when the second portable terminal user requests a PTT connection with the first portable terminal user. Therefore, the system enables the second portable terminal user to recognize the absent state of the first portable terminal user.

Abstract: A rendering apparatus and method are provided. The rendering method includes: reading a block, corresponding to a fragment, from among compressed blocks stored in a depth buffer, by considering frequency information corresponding to the fragment and prepared in advance; and performing a depth test for the fragment by considering the restored block.

Abstract: The present invention relates to a mobile communication terminal for Push To Talk (PTT) and a method for processing missed call information thereof, which allows a receiver to check why an originator requested the PTT telephone call during the absence of the receiver through missed call information. The missed call information includes the voice of the originator requesting the PTT call, and the voice of the originator is output when confirmation of the missed call information is requested.

Abstract: A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.

Abstract: A system, method and medium renders an object into a 3-dimensional (3D) graphic image. The rendering system includes a polygon processing unit to calculate a plurality of LOD values of a plurality of fragments corresponding to a plurality of vertices of a predetermined polygon, among a plurality of fragments constructing the predetermined polygon, a span conversion unit to interpolate a plurality of LOD values of remaining fragments apart from the plurality of fragments corresponding to the vertices of the predetermined polygon, using the calculated LOD values, and a texture mapping unit to map one of a plurality of textures with various resolutions to a corresponding fragment of the fragments constructing the predetermined polygon, on the basis of the LOD values interpolated by the span conversion unit.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ? in comparison to the existing pipelined divider.

Abstract: A graphics system and a memory device for three-dimensional (3D) graphics acceleration, and a method for 3D graphics processing, are provided. In a memory device in a graphics system for 3D graphics processing, a memory structure includes a first memory area allocated to a texture buffer for storing texture data, and a second memory area allocated to a frame buffer for storing frame data in pixels. A comparator controls the memory structure to operate as the texture buffer if an input address to the memory structure indicates the first memory area and controls the memory structure to operate as the frame buffer if the input address indicates the second memory area. If the memory structure operates as the frame buffer, an ALU performs depth comparison or alpha-blending on input frame data and frame data read from the frame buffer.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: A method and a device of consistency buffer for a high performance 3D graphic accelerator is disclosed to retain consistency without detecting any overlapping region in advance but determining an overlapping with respect to a rendered pixel.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ⅓ in comparison to the existing pipelined divider.

Abstract: A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced.