Abstract: A vehicle includes a memory configured to store predetermined points in time at which each of a plurality of tasks is to be performed, the plurality of tasks including a first task and a second task, and a detector configured to determine a malfunction of at least one processor of a plurality of processors performing the plurality of tasks, wherein the detector is configured to control the at least one processor to output trigger signals for the first task and the second task based on whether one of the first and second tasks is completed at its respective predetermined point in time.

Abstract: A vehicle includes a memory configured to store predetermined points in time at which each of a plurality of tasks is to be performed, the plurality of tasks including a first task and a second task, and a detector configured to determine a malfunction of at least one processor of a plurality of processors performing the plurality of tasks, wherein the detector is configured to control the at least one processor to output trigger signals for the first task and the second task based on whether one of the first and second tasks is completed at its respective predetermined point in time.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.

Abstract: An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.

Abstract: An interface device includes a transaction management unit, a buffer unit and a selection circuit. The transaction management unit selectively splits a transaction of a master device into a first sub-transaction and at least one remaining sub-transaction based on a size of the transaction. The buffer unit stores the remaining sub-transaction. The selection circuit selects one of the first sub-transaction and an output of the buffer unit in response to a select control signal.

Abstract: Provided is a data flow management device managing a plurality of data flows. The data flow management device transmits data flows received from a plurality of sources to be transmitted to a plurality of destinations. The data flow management device includes a plurality of buffers outputting data flows received from the sources; and a transmitting unit transmitting the data flows output from the buffers to the destinations. The buffers do not output at a same time any two data flows received from two different sources to be transmitted to a same destination.