Patents by Inventor Woo-dong Lee

Woo-dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9257309
    Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: February 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Jin Lee, Woo-Dong Lee
  • Patent number: 9245827
    Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
  • Patent number: 9177886
    Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: November 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Han Ko, Woo-Dong Lee, Tae-Sung Park
  • Publication number: 20150178770
    Abstract: The product advertisement management system is connected to an online marketplace and a marketplace system. An input interface unit receives advertisement bidding information which comprises a product number and a bidding price. An advertisement processing unit combines the advertisement bidding information with data of an advertiser product database (DB). A category-keyword matching unit receives product click information which comprises an input keyword, product categories and the numbers of product clicks and selects a matching category which is to be matched with the input keyword. A control unit displays product information, which corresponds to the matching category matched with a search keyword of the online marketplace or corresponds to a search category, in order of bidding price. The category-keyword matching unit selects a product category with a largest number of product clicks as the matching category among the product categories having the input keyword same.
    Type: Application
    Filed: January 9, 2014
    Publication date: June 25, 2015
    Applicant: NVISTA CO., LTD.
    Inventors: WOO DONG LEE, HYE RIM OH
  • Publication number: 20140242754
    Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.
    Type: Application
    Filed: April 10, 2014
    Publication date: August 28, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin LEE, Woo-Dong LEE
  • Publication number: 20140233292
    Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
  • Patent number: 8743582
    Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
  • Patent number: 8710677
    Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion.
    Type: Grant
    Filed: August 4, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin Lee, Woo-Dong Lee
  • Publication number: 20130270717
    Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.
    Type: Application
    Filed: November 8, 2012
    Publication date: October 17, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Han Ko, Woo-Dong Lee, Tae-Sung Park
  • Patent number: 8513802
    Abstract: A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum-Hee Ma, Woo-Dong Lee, Min-Seung Yoon, Ju-Il Choi, Sang-Sick Park, Son-Kwan Hwang
  • Publication number: 20130161836
    Abstract: Provided is a semiconductor package comprising a substrate, a semiconductor chip formed on the substrate, and an interposer including a plurality of segments which are separated from each other and arranged on the substrate to surround the semiconductor chip. And a stacked package for multiple chips including the semiconductor package with a plurality of segments of an interposer is provided.
    Type: Application
    Filed: August 13, 2012
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun-Dae YEOM, Young-Min KIM, Jong-Bo SHIM, Woo-Dong LEE
  • Publication number: 20130147062
    Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.
    Type: Application
    Filed: August 4, 2012
    Publication date: June 13, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin LEE, Woo-Dong LEE
  • Publication number: 20110292708
    Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
  • Publication number: 20110193229
    Abstract: A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 11, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keum-Hee Ma, Woo-Dong Lee, Min-Seung Yoon, Ju-il Choi, Sang-Sick Park, Son-Kwan Hwang
  • Patent number: 7589405
    Abstract: Provided are a memory card and a method of fabricating the memory card. The memory card includes: a printed circuit board including conductive wires exposed to at least a portion of an outer wall of the printed circuit board; at least one electronic device mounted on the printed circuit board; and a molding part sealing the at least one electronic device on the printed circuit board and the conductive wires exposed to the outer wall of the printed circuit board, and simultaneously exposing at least a portion of the outer wall of the printed circuit board.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: September 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Young Son, Woo-Dong Lee
  • Publication number: 20060116014
    Abstract: Provided are a memory card and a method of fabricating the memory card. The memory card includes: a printed circuit board including conductive wires exposed to at least a portion of an outer wall of the printed circuit board; at least one electronic device mounted on the printed circuit board; and a molding part sealing the at least one electronic device on the printed circuit board and the conductive wires exposed to the outer wall of the printed circuit board, and simultaneously exposing at least a portion of the outer wall of the printed circuit board.
    Type: Application
    Filed: November 23, 2005
    Publication date: June 1, 2006
    Inventors: Min-Young Son, Woo-Dong Lee
  • Patent number: 6812578
    Abstract: According to various embodiments of the present invention, a bonding pad structure of a semiconductor device reduces damage caused by thermo-mechanical stress in beam lead bonding. A method of fabricating an improved bonding pad structure is also provided. A polysilicon film plate is preferably formed between a bonding pad metal layer and a dielectric layer. The polysilicon film plate absorbs external thermo-mechanical stress and improves the durability of the bonding pad in a bond pull test (BPT). The bonding between the bonding pad metal layer and the dielectric layer is also improved. Other features and advantages are also provided.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: November 2, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin Kim, Tae-Gyeong Chung, Nam-Seog Kim, Woo-Dong Lee, Jin-Hyuk Lee
  • Publication number: 20030229373
    Abstract: An apparatus for preventing regeneration of endometrial synechia, which comprises: an air injection tube, into which air is injected from the outside; a drainage lumen tube for draining intrauterine residue and blood, in which the air injection tube is received; an air hole formed at one side around an upper end of the drainage lumen tube to eject the air passed through the air injection tube; and a balloon fixed to the drainage lumen tube while covering the air hole formed at one side around the upper end of the drainage lumen tube, the balloon being configured to be inflated to conform to a shape of a woman's uterus within the uterus by the air injected through the air injection tube and air hole. The balloon of the apparatus is adapted to uniformly and safely spread to the whole interior of the uterus including the intrauterine isthmus and fundus uteri, thereby preventing regeneration of endometrial synechia as well as minimizing inconvenience to patients.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 11, 2003
    Inventor: Woo-Dong Lee
  • Patent number: 6591789
    Abstract: A high-speed and high-pressure injection heat-generating device is provided, and enables liquid injected at a high speed and under a high pressure to become heated by the force of the friction and resistance generated from the collisions of liquid molecules as passing through a heating generating unit, and thus the heated liquid can be used for the purpose of heating water. By connecting a liquid circulating pump to a liquid feeding tube through which source liquid is supplied to the heating generating device on the outlet side of the liquid circulating pump and providing a tube with bends in the heating unit, where the tube includes a plurality projections closely formed on an inner surface thereof, more heating efficiency can be obtained. Therefore, the heat generating device can provide a heating source or hot water thereby obtaining a high temperature efficiency in variety of fields such as heating and hot water supply, without consuming energy sources like oil or gas.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 15, 2003
    Inventor: Woo-dong Lee
  • Publication number: 20020113313
    Abstract: According to various embodiments of the present invention, a bonding pad structure of a semiconductor device reduces damage caused by thermo-mechanical stress in beam lead bonding. A method of fabricating an improved bonding pad structure is also provided. A polysilicon film plate is preferably formed between a bonding pad metal layer and a dielectric layer. The polysilicon film plate absorbs external thermo-mechanical stress and improves the durability of the bonding pad in a bond pull test (BPT). The bonding between the bonding pad metal layer and the dielectric layer is also improved. Other features and advantages are also provided.
    Type: Application
    Filed: February 6, 2002
    Publication date: August 22, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shin Kim, Tae-Gyeong Chung, Nam-Seog Kim, Woo-Dong Lee, Jin-Hyuk Lee