Abstract: A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode signals are received.

Abstract: An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.

Abstract: A redundancy data storage circuit of a semiconductor memory includes a memory cell array; a write driver configured to write redundancy data in the memory cell array in response to a test signal; and a sense amplifier configured to detect and output the redundancy data written in the memory cell array in response to a read signal.

Abstract: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.

Abstract: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.

Abstract: A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid thermal annealing of a large-diameter wafer.

Abstract: The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.

Abstract: A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.

Abstract: An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.

Abstract: The present invention relates to a test control circuit controlling a test of an internal circuit and a semiconductor memory device including the same. The present invention provides a test control circuit having: an encoding unit encoding test mode signals input from the external and transferring them to global lines; a decoding unit decoding the signals transferred from the global lines; and a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable by combining the output signals of the decoding unit and an address designating a test mode item code.

Abstract: The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.

Abstract: A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode signals are received.

Abstract: A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid thermal annealing of a large-diameter wafer.

Abstract: The present invention relates to a test control circuit controlling a test of an internal circuit and a semiconductor memory device including the same. The present invention provides a test control circuit having: an encoding unit encoding test mode signals input from the external and transferring them to global lines; a decoding unit decoding the signals transferred from the global lines; and a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable by combining the output signals of the decoding unit and an address designating a test mode item code.

Abstract: An apparatus and method for feeding back Channel Quality Information (CQI) in a wireless communication system are provided. Total channels are grouped into certain number of groups according to downlink channel estimates. Group indexes are determined for the channels. Feedback information is generated using the group indexes of the channels and representative values of the groups. Then, the generated feedback information can be transmitted.

Abstract: A low-complexity dynamic channel allocation apparatus and method in a multi-carrier communication system are provided. In the low-complexity dynamic channel allocation method, subcarriers are initially allocated to total users and two users are selected from among all possible cases of two users out of the total users. The power gain of each of the subcarriers initially allocated to the selected two users is calculated, which can be generated by reallocating each subcarrier to the other user through subcarrier swapping. The power gains of the initially allocated subcarriers are ordered for each of the selected users and a pair of subcarriers with the greatest power gains for the two users are selected. Subcarriers are reallocated to the two users by swapping the selected subcarriers between the two users.