Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A printed circuit board (PCB) for transmitting a signal that includes a first layer, and a second layer disposed on the first layer. The first layer includes a first signal line to transmit the signal, and a first ground line and a second ground line disposed at both sides of the first signal line to be apart from the first signal line by a first distance. The second layer includes a second signal line to transmit the signal, and a third ground line and a fourth ground line disposed at both sides of the second signal line to be apart from the second signal line by a second distance. The third ground line or the fourth ground line is disposed on the first signal line.

Abstract: A test board for a semiconductor device tester having a modified input/output printed circuit pattern and a testing method using the same are provided. In an embodiment, a modified input/output printed circuit pattern is formed and controlled by a test program, wherein the modified input/output printed circuit pattern is divided into a drive terminal and a comparator terminal, one of the terminals being connected to one input pin of a device under test (DUT) and the other being connected to an output pin of the DUT, unlike a typical input/output printed circuit pattern of the test board that is formed to be connected to one output pin of a DUT. Thus, it is possible to increase the number of devices under parallel test and to test semiconductor memory devices having larger capacity by using limited resources of the tester.

Abstract: Provided is a system and method of testing a plurality of devices under test (DUTs) in parallel. The method includes preparing at least two DUTs having input/output signal pins connected in common to one input/output signal channel and having chip selection signal pins connected to a chip selection signal channel, which provides a chip selection signal to specify one output data among output data to be outputted through the commonly connected input/output channel. The method includes reading the outputted data specified by the chip selection signal through the commonly connected input/output signal channel from one of the devices under test selected by the chip selection signal.

Abstract: Provided is a system and method of testing a plurality of devices under test (DUTs) in parallel. The method includes preparing at least two DUTs having input/output signal pins connected in common to one input/output signal channel and having chip selection signal pins connected to a chip selection signal channel, which provides a chip selection signal to specify one output data among output data to be outputted through the commonly connected input/output channel. The method includes reading the outputted data specified by the chip selection signal through the commonly connected input/output signal channel from one of the devices under test selected by the chip selection signal.